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  1. Open On-Chip Debugger 0.10.0
  2. Licensed under GNU GPL v2
  3. For bug reports, read
  4.         http://openocd.org/doc/doxygen/bugs.html
  5. Info : auto-selecting first available session transport "hla_swd". To override use 'transport select <transport>'.
  6. Info : The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD
  7. adapter speed: 1000 kHz
  8. adapter_nsrst_delay: 100
  9. none separate
  10. Started by GNU MCU Eclipse
  11. Info : Unable to match requested speed 1000 kHz, using 950 kHz
  12. Info : Unable to match requested speed 1000 kHz, using 950 kHz
  13. Info : clock speed 950 kHz
  14. Info : STLINK v2 JTAG v29 API v2 SWIM v0 VID 0x0483 PID 0x3748
  15. Info : using stlink api v2
  16. Info : Target voltage: 2.903915
  17. Info : stm32f1x.cpu: hardware has 6 breakpoints, 4 watchpoints
  18. Info : accepting 'gdb' connection on tcp/3333
  19. Info : device id = 0x20036410
  20. Info : flash size = 64kbytes
  21. undefined debug reason 7 - target needs reset
  22. target halted due to debug-request, current mode: Thread
  23. xPSR: 0x01000000 pc: 0x08000154 msp: 0x20005000
  24. target halted due to breakpoint, current mode: Thread
  25. xPSR: 0x61000000 pc: 0x2000003a msp: 0x20005000
  26. target halted due to debug-request, current mode: Thread
  27. xPSR: 0x01000000 pc: 0x08000154 msp: 0x20005000
  28. target halted due to debug-request, current mode: Thread
  29. xPSR: 0x21000000 pc: 0x080002ba msp: 0x20004ff0
  30. ===== arm v7m registers
  31. (0) r0 (/32): 0x20000014
  32. (1) r1 (/32): 0x00000000
  33. (2) r2 (/32): 0x00002000
  34. (3) r3 (/32): 0x40011000
  35. (4) r4 (/32): 0x20000014
  36. (5) r5 (/32): 0x00000032
  37. (6) r6 (/32): 0x000003E1
  38. (7) r7 (/32): 0x00F00000
  39. (8) r8 (/32): 0x08000400
  40. (9) r9 (/32): 0xEFFFDFD5
  41. (10) r10 (/32): 0xCFFD76C2
  42. (11) r11 (/32): 0x64D780B8
  43. (12) r12 (/32): 0x00002000
  44. (13) sp (/32): 0x20004FF0
  45. (14) lr (/32): 0xFFFFFFFF
  46. (15) pc (/32): 0x080002BA
  47. (16) xPSR (/32): 0x21000000
  48. (17) msp (/32): 0x20004FF0
  49. (18) psp (/32): 0x08687AE8
  50. (19) primask (/1): 0x00
  51. (20) basepri (/8): 0x00
  52. (21) faultmask (/1): 0x00
  53. (22) control (/2): 0x00
  54. ===== Cortex-M DWT registers
  55. (23) dwt_ctrl (/32)
  56. (24) dwt_cyccnt (/32)
  57. (25) dwt_0_comp (/32)
  58. (26) dwt_0_mask (/4)
  59. (27) dwt_0_function (/32)
  60. (28) dwt_1_comp (/32)
  61. (29) dwt_1_mask (/4)
  62. (30) dwt_1_function (/32)
  63. (31) dwt_2_comp (/32)
  64. (32) dwt_2_mask (/4)
  65. (33) dwt_2_function (/32)
  66. (34) dwt_3_comp (/32)
  67. (35) dwt_3_mask (/4)
  68. (36) dwt_3_function (/32)

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