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Re: Re: Bez tytułu

z Beige Parrot, 9 miesiące temu, napisane w Plain Text, wyświetlone 125 razy. [paste_expire] 1 miesiąc. Ta wklejka jest odpowiedzią na Re: Bez tytułu z Denim Mockingbird - Pokaż różnice
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  1. # 0 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-14N0261I-headless.dts"
  2. # 0 "<built-in>"
  3. # 0 "<command-line>"
  4. # 1 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-14N0261I-headless.dts"
  5. # 14 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-14N0261I-headless.dts"
  6. # 1 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-14N0261I-base.dtsi" 1
  7. # 14 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-14N0261I-base.dtsi"
  8. # 1 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-base.dtsi" 1
  9. # 14 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-base.dtsi"
  10. /dts-v1/;
  11.  
  12. # 1 "arch/arm64/boot/dts/msc/imx8mm/msc-imx8mm.dtsi" 1
  13. # 14 "arch/arm64/boot/dts/msc/imx8mm/msc-imx8mm.dtsi"
  14. # 1 "./scripts/dtc/include-prefixes/dt-bindings/reset/imx8mm-dispmix.h" 1
  15. # 15 "arch/arm64/boot/dts/msc/imx8mm/msc-imx8mm.dtsi" 2
  16. # 1 "arch/arm64/boot/dts/msc/imx8mm/../../freescale/imx8mm.dtsi" 1
  17.  
  18.  
  19.  
  20.  
  21.  
  22. # 1 "./scripts/dtc/include-prefixes/dt-bindings/clock/imx8mm-clock.h" 1
  23. # 7 "arch/arm64/boot/dts/msc/imx8mm/../../freescale/imx8mm.dtsi" 2
  24. # 1 "./scripts/dtc/include-prefixes/dt-bindings/gpio/gpio.h" 1
  25. # 8 "arch/arm64/boot/dts/msc/imx8mm/../../freescale/imx8mm.dtsi" 2
  26. # 1 "./scripts/dtc/include-prefixes/dt-bindings/input/input.h" 1
  27. # 13 "./scripts/dtc/include-prefixes/dt-bindings/input/input.h"
  28. # 1 "./scripts/dtc/include-prefixes/dt-bindings/input/linux-event-codes.h" 1
  29. # 14 "./scripts/dtc/include-prefixes/dt-bindings/input/input.h" 2
  30. # 9 "arch/arm64/boot/dts/msc/imx8mm/../../freescale/imx8mm.dtsi" 2
  31. # 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 1
  32. # 9 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h"
  33. # 1 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/irq.h" 1
  34. # 10 "./scripts/dtc/include-prefixes/dt-bindings/interrupt-controller/arm-gic.h" 2
  35. # 10 "arch/arm64/boot/dts/msc/imx8mm/../../freescale/imx8mm.dtsi" 2
  36. # 1 "./scripts/dtc/include-prefixes/dt-bindings/power/imx8mm-power.h" 1
  37. # 11 "arch/arm64/boot/dts/msc/imx8mm/../../freescale/imx8mm.dtsi" 2
  38. # 1 "./scripts/dtc/include-prefixes/dt-bindings/reset/imx8mq-reset.h" 1
  39. # 12 "arch/arm64/boot/dts/msc/imx8mm/../../freescale/imx8mm.dtsi" 2
  40. # 1 "./scripts/dtc/include-prefixes/dt-bindings/thermal/thermal.h" 1
  41. # 13 "arch/arm64/boot/dts/msc/imx8mm/../../freescale/imx8mm.dtsi" 2
  42.  
  43. # 1 "arch/arm64/boot/dts/msc/imx8mm/../../freescale/imx8mm-pinfunc.h" 1
  44. # 15 "arch/arm64/boot/dts/msc/imx8mm/../../freescale/imx8mm.dtsi" 2
  45.  
  46. / {
  47.  interrupt-parent = <&gic>;
  48.  #address-cells = <2>;
  49.  #size-cells = <2>;
  50.  
  51.  aliases {
  52.   ethernet0 = &fec1;
  53.   gpio0 = &gpio1;
  54.   gpio1 = &gpio2;
  55.   gpio2 = &gpio3;
  56.   gpio3 = &gpio4;
  57.   gpio4 = &gpio5;
  58.   i2c0 = &i2c1;
  59.   i2c1 = &i2c2;
  60.   i2c2 = &i2c3;
  61.   i2c3 = &i2c4;
  62.   mmc0 = &usdhc1;
  63.   mmc1 = &usdhc2;
  64.   mmc2 = &usdhc3;
  65.   serial0 = &uart1;
  66.   serial1 = &uart2;
  67.   serial2 = &uart3;
  68.   serial3 = &uart4;
  69.   spi0 = &ecspi1;
  70.   spi1 = &ecspi2;
  71.   spi2 = &ecspi3;
  72.   gpu0 = &gpu_3d;
  73.   gpu = &gpu_3d;
  74.  };
  75.  
  76.  cpus {
  77.   #address-cells = <1>;
  78.   #size-cells = <0>;
  79.  
  80.   idle-states {
  81.    entry-method = "psci";
  82.  
  83.    cpu_pd_wait: cpu-pd-wait {
  84.     compatible = "arm,idle-state";
  85.     arm,psci-suspend-param = <0x0010033>;
  86.     local-timer-stop;
  87.     entry-latency-us = <1000>;
  88.     exit-latency-us = <700>;
  89.     min-residency-us = <2700>;
  90.    };
  91.   };
  92.  
  93.   A53_0: cpu@0 {
  94.    device_type = "cpu";
  95.    compatible = "arm,cortex-a53";
  96.    reg = <0x0>;
  97.    clock-latency = <61036>;
  98.    clocks = <&clk 215>;
  99.    enable-method = "psci";
  100.    i-cache-size = <0x8000>;
  101.    i-cache-line-size = <64>;
  102.    i-cache-sets = <256>;
  103.    d-cache-size = <0x8000>;
  104.    d-cache-line-size = <64>;
  105.    d-cache-sets = <128>;
  106.    next-level-cache = <&A53_L2>;
  107.    operating-points-v2 = <&a53_opp_table>;
  108.    nvmem-cells = <&cpu_speed_grade>;
  109.    nvmem-cell-names = "speed_grade";
  110.    cpu-idle-states = <&cpu_pd_wait>;
  111.    #cooling-cells = <2>;
  112.   };
  113.  
  114.   A53_1: cpu@1 {
  115.    device_type = "cpu";
  116.    compatible = "arm,cortex-a53";
  117.    reg = <0x1>;
  118.    clock-latency = <61036>;
  119.    clocks = <&clk 215>;
  120.    enable-method = "psci";
  121.    i-cache-size = <0x8000>;
  122.    i-cache-line-size = <64>;
  123.    i-cache-sets = <256>;
  124.    d-cache-size = <0x8000>;
  125.    d-cache-line-size = <64>;
  126.    d-cache-sets = <128>;
  127.    next-level-cache = <&A53_L2>;
  128.    operating-points-v2 = <&a53_opp_table>;
  129.    cpu-idle-states = <&cpu_pd_wait>;
  130.    #cooling-cells = <2>;
  131.   };
  132.  
  133.   A53_2: cpu@2 {
  134.    device_type = "cpu";
  135.    compatible = "arm,cortex-a53";
  136.    reg = <0x2>;
  137.    clock-latency = <61036>;
  138.    clocks = <&clk 215>;
  139.    enable-method = "psci";
  140.    i-cache-size = <0x8000>;
  141.    i-cache-line-size = <64>;
  142.    i-cache-sets = <256>;
  143.    d-cache-size = <0x8000>;
  144.    d-cache-line-size = <64>;
  145.    d-cache-sets = <128>;
  146.    next-level-cache = <&A53_L2>;
  147.    operating-points-v2 = <&a53_opp_table>;
  148.    cpu-idle-states = <&cpu_pd_wait>;
  149.    #cooling-cells = <2>;
  150.   };
  151.  
  152.   A53_3: cpu@3 {
  153.    device_type = "cpu";
  154.    compatible = "arm,cortex-a53";
  155.    reg = <0x3>;
  156.    clock-latency = <61036>;
  157.    clocks = <&clk 215>;
  158.    enable-method = "psci";
  159.    i-cache-size = <0x8000>;
  160.    i-cache-line-size = <64>;
  161.    i-cache-sets = <256>;
  162.    d-cache-size = <0x8000>;
  163.    d-cache-line-size = <64>;
  164.    d-cache-sets = <128>;
  165.    next-level-cache = <&A53_L2>;
  166.    operating-points-v2 = <&a53_opp_table>;
  167.    cpu-idle-states = <&cpu_pd_wait>;
  168.    #cooling-cells = <2>;
  169.   };
  170.  
  171.   A53_L2: l2-cache0 {
  172.    compatible = "cache";
  173.    cache-level = <2>;
  174.    cache-size = <0x80000>;
  175.    cache-line-size = <64>;
  176.    cache-sets = <512>;
  177.   };
  178.  };
  179.  
  180.  a53_opp_table: opp-table {
  181.   compatible = "operating-points-v2";
  182.   opp-shared;
  183.  
  184.   opp-1200000000 {
  185.    opp-hz = /bits/ 64 <1200000000>;
  186.    opp-microvolt = <850000>;
  187.    opp-supported-hw = <0xe>, <0x7>;
  188.    clock-latency-ns = <150000>;
  189.    opp-suspend;
  190.   };
  191.  
  192.   opp-1600000000 {
  193.    opp-hz = /bits/ 64 <1600000000>;
  194.    opp-microvolt = <950000>;
  195.    opp-supported-hw = <0xc>, <0x7>;
  196.    clock-latency-ns = <150000>;
  197.    opp-suspend;
  198.   };
  199.  
  200.   opp-1800000000 {
  201.    opp-hz = /bits/ 64 <1800000000>;
  202.    opp-microvolt = <1000000>;
  203.    opp-supported-hw = <0x8>, <0x3>;
  204.    clock-latency-ns = <150000>;
  205.    opp-suspend;
  206.   };
  207.  };
  208.  
  209.  osc_32k: clock-osc-32k {
  210.   compatible = "fixed-clock";
  211.   #clock-cells = <0>;
  212.   clock-frequency = <32768>;
  213.   clock-output-names = "osc_32k";
  214.  };
  215.  
  216.  osc_24m: clock-osc-24m {
  217.   compatible = "fixed-clock";
  218.   #clock-cells = <0>;
  219.   clock-frequency = <24000000>;
  220.   clock-output-names = "osc_24m";
  221.  };
  222.  
  223.  clk_ext1: clock-ext1 {
  224.   compatible = "fixed-clock";
  225.   #clock-cells = <0>;
  226.   clock-frequency = <133000000>;
  227.   clock-output-names = "clk_ext1";
  228.  };
  229.  
  230.  clk_ext2: clock-ext2 {
  231.   compatible = "fixed-clock";
  232.   #clock-cells = <0>;
  233.   clock-frequency = <133000000>;
  234.   clock-output-names = "clk_ext2";
  235.  };
  236.  
  237.  clk_ext3: clock-ext3 {
  238.   compatible = "fixed-clock";
  239.   #clock-cells = <0>;
  240.   clock-frequency = <133000000>;
  241.   clock-output-names = "clk_ext3";
  242.  };
  243.  
  244.  clk_ext4: clock-ext4 {
  245.   compatible = "fixed-clock";
  246.   #clock-cells = <0>;
  247.   clock-frequency= <133000000>;
  248.   clock-output-names = "clk_ext4";
  249.  };
  250.  
  251.  psci {
  252.   compatible = "arm,psci-1.0";
  253.   method = "smc";
  254.  };
  255.  
  256.  pmu {
  257.   compatible = "arm,cortex-a53-pmu";
  258.   interrupts = <1 7
  259.         ((((1 << (4)) - 1) << 8) | 4)>;
  260.  };
  261.  
  262.  timer {
  263.   compatible = "arm,armv8-timer";
  264.   interrupts = <1 13 ((((1 << (4)) - 1) << 8) | 8)>,
  265.         <1 14 ((((1 << (4)) - 1) << 8) | 8)>,
  266.         <1 11 ((((1 << (4)) - 1) << 8) | 8)>,
  267.         <1 10 ((((1 << (4)) - 1) << 8) | 8)>;
  268.   clock-frequency = <8000000>;
  269.   arm,no-tick-in-suspend;
  270.  };
  271.  
  272.  thermal-zones {
  273.   cpu-thermal {
  274.    polling-delay-passive = <250>;
  275.    polling-delay = <2000>;
  276.    thermal-sensors = <&tmu>;
  277.    trips {
  278.     cpu_alert0: trip0 {
  279.      temperature = <85000>;
  280.      hysteresis = <2000>;
  281.      type = "passive";
  282.     };
  283.  
  284.     cpu_crit0: trip1 {
  285.      temperature = <95000>;
  286.      hysteresis = <2000>;
  287.      type = "critical";
  288.     };
  289.    };
  290.  
  291.    cooling-maps {
  292.     map0 {
  293.      trip = <&cpu_alert0>;
  294.      cooling-device =
  295.       <&A53_0 (~0) (~0)>,
  296.       <&A53_1 (~0) (~0)>,
  297.       <&A53_2 (~0) (~0)>,
  298.       <&A53_3 (~0) (~0)>;
  299.     };
  300.    };
  301.   };
  302.  };
  303.  
  304.  usbphynop1: usbphynop1 {
  305.   #phy-cells = <0>;
  306.   compatible = "usb-nop-xceiv";
  307.   clocks = <&clk 132>;
  308.   assigned-clocks = <&clk 132>;
  309.   assigned-clock-parents = <&clk 50>;
  310.   clock-names = "main_clk";
  311.  };
  312.  
  313.  usbphynop2: usbphynop2 {
  314.   #phy-cells = <0>;
  315.   compatible = "usb-nop-xceiv";
  316.   clocks = <&clk 132>;
  317.   assigned-clocks = <&clk 132>;
  318.   assigned-clock-parents = <&clk 50>;
  319.   clock-names = "main_clk";
  320.  };
  321.  
  322.  soc@0 {
  323.   compatible = "fsl,imx8mm-soc", "simple-bus";
  324.   #address-cells = <1>;
  325.   #size-cells = <1>;
  326.   ranges = <0x0 0x0 0x0 0x3e000000>;
  327.   dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
  328.   nvmem-cells = <&imx8mm_uid>;
  329.   nvmem-cell-names = "soc_unique_id";
  330.  
  331.   aips1: bus@30000000 {
  332.    compatible = "fsl,aips-bus", "simple-bus";
  333.    reg = <0x30000000 0x400000>;
  334.    #address-cells = <1>;
  335.    #size-cells = <1>;
  336.    ranges = <0x30000000 0x30000000 0x400000>;
  337.  
  338.    spba2: spba-bus@30000000 {
  339.     compatible = "fsl,spba-bus", "simple-bus";
  340.     #address-cells = <1>;
  341.     #size-cells = <1>;
  342.     reg = <0x30000000 0x100000>;
  343.     ranges;
  344.  
  345.     sai1: sai@30010000 {
  346.      #sound-dai-cells = <0>;
  347.      compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
  348.      reg = <0x30010000 0x10000>;
  349.      interrupts = <0 95 4>;
  350.      clocks = <&clk 177>,
  351.        <&clk 176>,
  352.        <&clk 0>, <&clk 0>;
  353.      clock-names = "bus", "mclk1", "mclk2", "mclk3";
  354.      dmas = <&sdma2 0 2 0>, <&sdma2 1 2 0>;
  355.      dma-names = "rx", "tx";
  356.      status = "disabled";
  357.     };
  358.  
  359.     sai2: sai@30020000 {
  360.      #sound-dai-cells = <0>;
  361.      compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
  362.      reg = <0x30020000 0x10000>;
  363.      interrupts = <0 96 4>;
  364.      clocks = <&clk 179>,
  365.       <&clk 178>,
  366.       <&clk 0>, <&clk 0>;
  367.      clock-names = "bus", "mclk1", "mclk2", "mclk3";
  368.      dmas = <&sdma2 2 2 0>, <&sdma2 3 2 0>;
  369.      dma-names = "rx", "tx";
  370.      status = "disabled";
  371.     };
  372.  
  373.     sai3: sai@30030000 {
  374.      #sound-dai-cells = <0>;
  375.      compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
  376.      reg = <0x30030000 0x10000>;
  377.      interrupts = <0 50 4>;
  378.      clocks = <&clk 181>,
  379.        <&clk 180>,
  380.        <&clk 0>, <&clk 0>;
  381.      clock-names = "bus", "mclk1", "mclk2", "mclk3";
  382.      dmas = <&sdma2 4 2 0>, <&sdma2 5 2 0>;
  383.      dma-names = "rx", "tx";
  384.      status = "disabled";
  385.     };
  386.  
  387.     sai5: sai@30050000 {
  388.      #sound-dai-cells = <0>;
  389.      compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
  390.      reg = <0x30050000 0x10000>;
  391.      interrupts = <0 90 4>;
  392.      clocks = <&clk 185>,
  393.        <&clk 184>,
  394.        <&clk 0>, <&clk 0>;
  395.      clock-names = "bus", "mclk1", "mclk2", "mclk3";
  396.      dmas = <&sdma2 8 2 0>, <&sdma2 9 2 0>;
  397.      dma-names = "rx", "tx";
  398.      status = "disabled";
  399.     };
  400.  
  401.     sai6: sai@30060000 {
  402.      #sound-dai-cells = <0>;
  403.      compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
  404.      reg = <0x30060000 0x10000>;
  405.      interrupts = <0 90 4>;
  406.      clocks = <&clk 187>,
  407.        <&clk 186>,
  408.        <&clk 0>, <&clk 0>;
  409.      clock-names = "bus", "mclk1", "mclk2", "mclk3";
  410.      dmas = <&sdma2 10 2 0>, <&sdma2 11 2 0>;
  411.      dma-names = "rx", "tx";
  412.      status = "disabled";
  413.     };
  414.  
  415.     micfil: audio-controller@30080000 {
  416.      compatible = "fsl,imx8mm-micfil";
  417.      reg = <0x30080000 0x10000>;
  418.      interrupts = <0 109 4>,
  419.            <0 110 4>,
  420.            <0 44 4>,
  421.            <0 45 4>;
  422.      clocks = <&clk 216>,
  423.        <&clk 203>,
  424.        <&clk 38>,
  425.        <&clk 39>,
  426.        <&clk 6>;
  427.      clock-names = "ipg_clk", "ipg_clk_app",
  428.             "pll8k", "pll11k", "clkext3";
  429.      dmas = <&sdma2 24 25 0x80000000>;
  430.      dma-names = "rx";
  431.      status = "disabled";
  432.     };
  433.  
  434.     spdif1: spdif@30090000 {
  435.      compatible = "fsl,imx35-spdif";
  436.      reg = <0x30090000 0x10000>;
  437.      interrupts = <0 6 4>;
  438.      clocks = <&clk 94>,
  439.        <&clk 2>,
  440.        <&clk 114>,
  441.        <&clk 0>,
  442.        <&clk 0>,
  443.        <&clk 0>,
  444.        <&clk 94>,
  445.        <&clk 0>,
  446.        <&clk 0>,
  447.        <&clk 0>;
  448.      clock-names = "core", "rxtx0",
  449.             "rxtx1", "rxtx2",
  450.             "rxtx3", "rxtx4",
  451.             "rxtx5", "rxtx6",
  452.             "rxtx7", "spba";
  453.      dmas = <&sdma2 28 18 0>, <&sdma2 29 18 0>;
  454.      dma-names = "rx", "tx";
  455.      status = "disabled";
  456.     };
  457.    };
  458.  
  459.    gpio1: gpio@30200000 {
  460.     compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
  461.     reg = <0x30200000 0x10000>;
  462.     interrupts = <0 64 4>,
  463.           <0 65 4>;
  464.     clocks = <&clk 223>;
  465.     gpio-controller;
  466.     #gpio-cells = <2>;
  467.     interrupt-controller;
  468.     #interrupt-cells = <2>;
  469.     gpio-ranges = <&iomuxc 0 10 30>;
  470.    };
  471.  
  472.    gpio2: gpio@30210000 {
  473.     compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
  474.     reg = <0x30210000 0x10000>;
  475.     interrupts = <0 66 4>,
  476.           <0 67 4>;
  477.     clocks = <&clk 224>;
  478.     gpio-controller;
  479.     #gpio-cells = <2>;
  480.     interrupt-controller;
  481.     #interrupt-cells = <2>;
  482.     gpio-ranges = <&iomuxc 0 40 21>;
  483.    };
  484.  
  485.    gpio3: gpio@30220000 {
  486.     compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
  487.     reg = <0x30220000 0x10000>;
  488.     interrupts = <0 68 4>,
  489.           <0 69 4>;
  490.     clocks = <&clk 225>;
  491.     gpio-controller;
  492.     #gpio-cells = <2>;
  493.     interrupt-controller;
  494.     #interrupt-cells = <2>;
  495.     gpio-ranges = <&iomuxc 0 61 26>;
  496.    };
  497.  
  498.    gpio4: gpio@30230000 {
  499.     compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
  500.     reg = <0x30230000 0x10000>;
  501.     interrupts = <0 70 4>,
  502.           <0 71 4>;
  503.     clocks = <&clk 226>;
  504.     gpio-controller;
  505.     #gpio-cells = <2>;
  506.     interrupt-controller;
  507.     #interrupt-cells = <2>;
  508.     gpio-ranges = <&iomuxc 0 87 32>;
  509.    };
  510.  
  511.    gpio5: gpio@30240000 {
  512.     compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
  513.     reg = <0x30240000 0x10000>;
  514.     interrupts = <0 72 4>,
  515.           <0 73 4>;
  516.     clocks = <&clk 227>;
  517.     gpio-controller;
  518.     #gpio-cells = <2>;
  519.     interrupt-controller;
  520.     #interrupt-cells = <2>;
  521.     gpio-ranges = <&iomuxc 0 119 30>;
  522.    };
  523.  
  524.    tmu: tmu@30260000 {
  525.     compatible = "fsl,imx8mm-tmu";
  526.     reg = <0x30260000 0x10000>;
  527.     clocks = <&clk 209>;
  528.     #thermal-sensor-cells = <0>;
  529.    };
  530.  
  531.    wdog1: watchdog@30280000 {
  532.     compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
  533.     reg = <0x30280000 0x10000>;
  534.     interrupts = <0 78 4>;
  535.     clocks = <&clk 196>;
  536.     status = "disabled";
  537.    };
  538.  
  539.    wdog2: watchdog@30290000 {
  540.     compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
  541.     reg = <0x30290000 0x10000>;
  542.     interrupts = <0 79 4>;
  543.     clocks = <&clk 197>;
  544.     status = "disabled";
  545.    };
  546.  
  547.    wdog3: watchdog@302a0000 {
  548.     compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
  549.     reg = <0x302a0000 0x10000>;
  550.     interrupts = <0 10 4>;
  551.     clocks = <&clk 198>;
  552.     status = "disabled";
  553.    };
  554.  
  555.    sdma2: dma-controller@302c0000 {
  556.     compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
  557.     reg = <0x302c0000 0x10000>;
  558.     interrupts = <0 103 4>;
  559.     clocks = <&clk 212>,
  560.       <&clk 212>;
  561.     clock-names = "ipg", "ahb";
  562.     #dma-cells = <3>;
  563.     fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
  564.    };
  565.  
  566.    sdma3: dma-controller@302b0000 {
  567.     compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
  568.     reg = <0x302b0000 0x10000>;
  569.     interrupts = <0 34 4>;
  570.     clocks = <&clk 213>,
  571.      <&clk 213>;
  572.     clock-names = "ipg", "ahb";
  573.     #dma-cells = <3>;
  574.     fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
  575.    };
  576.  
  577.    iomuxc: pinctrl@30330000 {
  578.     compatible = "fsl,imx8mm-iomuxc";
  579.     reg = <0x30330000 0x10000>;
  580.    };
  581.  
  582.    gpr: iomuxc-gpr@30340000 {
  583.     compatible = "fsl,imx8mm-iomuxc-gpr", "fsl,imx6q-iomuxc-gpr", "syscon";
  584.     reg = <0x30340000 0x10000>;
  585.    };
  586.  
  587.    ocotp: efuse@30350000 {
  588.     compatible = "fsl,imx8mm-ocotp", "syscon";
  589.     reg = <0x30350000 0x10000>;
  590.     clocks = <&clk 168>;
  591.  
  592.     #address-cells = <1>;
  593.     #size-cells = <1>;
  594.  
  595.     imx8mm_uid: unique-id@410 {
  596.      reg = <0x4 0x8>;
  597.     };
  598.  
  599.     cpu_speed_grade: speed-grade@10 {
  600.      reg = <0x10 4>;
  601.     };
  602.  
  603.     fec_mac_address: mac-address@90 {
  604.      reg = <0x90 6>;
  605.     };
  606.    };
  607.  
  608.    anatop: anatop@30360000 {
  609.     compatible = "fsl,imx8mm-anatop", "syscon";
  610.     reg = <0x30360000 0x10000>;
  611.    };
  612.  
  613.    snvs: snvs@30370000 {
  614.     compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
  615.     reg = <0x30370000 0x10000>;
  616.  
  617.     snvs_rtc: snvs-rtc-lp {
  618.      compatible = "fsl,sec-v4.0-mon-rtc-lp";
  619.      regmap = <&snvs>;
  620.      offset = <0x34>;
  621.      interrupts = <0 19 4>,
  622.            <0 20 4>;
  623.      clocks = <&clk 228>;
  624.      clock-names = "snvs-rtc";
  625.     };
  626.  
  627.     snvs_pwrkey: snvs-powerkey {
  628.      compatible = "fsl,sec-v4.0-pwrkey";
  629.      regmap = <&snvs>;
  630.      interrupts = <0 4 4>;
  631.      clocks = <&clk 228>;
  632.      clock-names = "snvs-pwrkey";
  633.      linux,keycode = <116>;
  634.      wakeup-source;
  635.      status = "disabled";
  636.     };
  637.    };
  638.  
  639.    clk: clock-controller@30380000 {
  640.     compatible = "fsl,imx8mm-ccm";
  641.     reg = <0x30380000 0x10000>;
  642.     #clock-cells = <1>;
  643.     clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>,
  644.       <&clk_ext3>, <&clk_ext4>;
  645.     clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
  646.            "clk_ext3", "clk_ext4";
  647.     assigned-clocks = <&clk 66>,
  648.       <&clk 251>,
  649.       <&clk 91>,
  650.       <&clk 94>,
  651.       <&clk 96>,
  652.       <&clk 27>,
  653.       <&clk 20>,
  654.       <&clk 18>;
  655.     assigned-clock-parents = <&clk 56>,
  656.         <&clk 44>,
  657.         <&clk 47>,
  658.         <&clk 56>;
  659.     assigned-clock-rates = <0>, <0>, <0>,
  660.        <400000000>,
  661.        <400000000>,
  662.        <750000000>,
  663.        <594000000>,
  664.        <393216000>;
  665.    };
  666.  
  667.    src: reset-controller@30390000 {
  668.     compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
  669.     reg = <0x30390000 0x10000>;
  670.     interrupts = <0 89 4>;
  671.     #reset-cells = <1>;
  672.    };
  673.  
  674.    gpc: gpc@303a0000 {
  675.     compatible = "fsl,imx8mm-gpc";
  676.     reg = <0x303a0000 0x10000>;
  677.     interrupts = <0 87 4>;
  678.     interrupt-parent = <&gic>;
  679.     interrupt-controller;
  680.     #interrupt-cells = <3>;
  681.  
  682.     pgc {
  683.      #address-cells = <1>;
  684.      #size-cells = <0>;
  685.  
  686.      pgc_hsiomix: power-domain@0 {
  687.       #power-domain-cells = <0>;
  688.       reg = <0>;
  689.       clocks = <&clk 88>;
  690.       assigned-clocks = <&clk 88>;
  691.       assigned-clock-parents = <&clk 64>;
  692.      };
  693.  
  694.      pgc_pcie: power-domain@1 {
  695.       #power-domain-cells = <0>;
  696.       reg = <1>;
  697.       power-domains = <&pgc_hsiomix>;
  698.       clocks = <&clk 169>;
  699.      };
  700.  
  701.      pgc_otg1: power-domain@2 {
  702.       #power-domain-cells = <0>;
  703.       reg = <2>;
  704.       power-domains = <&pgc_hsiomix>;
  705.      };
  706.  
  707.      pgc_otg2: power-domain@3 {
  708.       #power-domain-cells = <0>;
  709.       reg = <3>;
  710.       power-domains = <&pgc_hsiomix>;
  711.      };
  712.  
  713.      pgc_gpumix: power-domain@4 {
  714.       #power-domain-cells = <0>;
  715.       reg = <4>;
  716.       clocks = <&clk 200>,
  717.         <&clk 90>;
  718.       assigned-clocks = <&clk 89>,
  719.           <&clk 90>;
  720.       assigned-clock-parents = <&clk 56>,
  721.           <&clk 56>;
  722.       assigned-clock-rates = <800000000>, <400000000>;
  723.      };
  724.  
  725.      pgc_gpu: power-domain@5 {
  726.       #power-domain-cells = <0>;
  727.       reg = <5>;
  728.       clocks = <&clk 90>,
  729.         <&clk 200>,
  730.         <&clk 217>,
  731.         <&clk 193>;
  732.       resets = <&src 32>;
  733.       power-domains = <&pgc_gpumix>;
  734.      };
  735.  
  736.      pgc_vpumix: power-domain@6 {
  737.       #power-domain-cells = <0>;
  738.       reg = <6>;
  739.       clocks = <&clk 210>;
  740.       assigned-clocks = <&clk 84>;
  741.       assigned-clock-parents = <&clk 56>;
  742.      };
  743.  
  744.      pgc_vpu_g1: power-domain@7 {
  745.       #power-domain-cells = <0>;
  746.       reg = <7>;
  747.      };
  748.  
  749.      pgc_vpu_g2: power-domain@8 {
  750.       #power-domain-cells = <0>;
  751.       reg = <8>;
  752.      };
  753.  
  754.      pgc_vpu_h1: power-domain@9 {
  755.       #power-domain-cells = <0>;
  756.       reg = <9>;
  757.      };
  758.  
  759.      pgc_dispmix: power-domain@10 {
  760.       #power-domain-cells = <0>;
  761.       reg = <10>;
  762.       clocks = <&clk 206>,
  763.         <&clk 205>;
  764.       assigned-clocks = <&clk 85>,
  765.           <&clk 86>;
  766.       assigned-clock-parents = <&clk 65>,
  767.           <&clk 56>;
  768.       assigned-clock-rates = <500000000>, <200000000>;
  769.      };
  770.  
  771.      pgc_mipi: power-domain@11 {
  772.       #power-domain-cells = <0>;
  773.       reg = <11>;
  774.      };
  775.     };
  776.    };
  777.   };
  778.  
  779.   aips2: bus@30400000 {
  780.    compatible = "fsl,aips-bus", "simple-bus";
  781.    reg = <0x30400000 0x400000>;
  782.    #address-cells = <1>;
  783.    #size-cells = <1>;
  784.    ranges = <0x30400000 0x30400000 0x400000>;
  785.  
  786.    pwm1: pwm@30660000 {
  787.     compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
  788.     reg = <0x30660000 0x10000>;
  789.     interrupts = <0 81 4>;
  790.     clocks = <&clk 170>,
  791.      <&clk 170>;
  792.     clock-names = "ipg", "per";
  793.     #pwm-cells = <3>;
  794.     status = "disabled";
  795.    };
  796.  
  797.    pwm2: pwm@30670000 {
  798.     compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
  799.     reg = <0x30670000 0x10000>;
  800.     interrupts = <0 82 4>;
  801.     clocks = <&clk 171>,
  802.       <&clk 171>;
  803.     clock-names = "ipg", "per";
  804.     #pwm-cells = <3>;
  805.     status = "disabled";
  806.    };
  807.  
  808.    pwm3: pwm@30680000 {
  809.     compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
  810.     reg = <0x30680000 0x10000>;
  811.     interrupts = <0 83 4>;
  812.     clocks = <&clk 172>,
  813.       <&clk 172>;
  814.     clock-names = "ipg", "per";
  815.     #pwm-cells = <3>;
  816.     status = "disabled";
  817.    };
  818.  
  819.    pwm4: pwm@30690000 {
  820.     compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
  821.     reg = <0x30690000 0x10000>;
  822.     interrupts = <0 84 4>;
  823.     clocks = <&clk 173>,
  824.       <&clk 173>;
  825.     clock-names = "ipg", "per";
  826.     #pwm-cells = <3>;
  827.     status = "disabled";
  828.    };
  829.  
  830.    system_counter: timer@306a0000 {
  831.     compatible = "nxp,sysctr-timer";
  832.     reg = <0x306a0000 0x20000>;
  833.     interrupts = <0 47 4>;
  834.     clocks = <&osc_24m>;
  835.     clock-names = "per";
  836.    };
  837.   };
  838.  
  839.   aips3: bus@30800000 {
  840.    compatible = "fsl,aips-bus", "simple-bus";
  841.    reg = <0x30800000 0x400000>;
  842.    #address-cells = <1>;
  843.    #size-cells = <1>;
  844.    ranges = <0x30800000 0x30800000 0x400000>,
  845.      <0x8000000 0x8000000 0x10000000>;
  846.  
  847.    spba1: spba-bus@30800000 {
  848.     compatible = "fsl,spba-bus", "simple-bus";
  849.     #address-cells = <1>;
  850.     #size-cells = <1>;
  851.     reg = <0x30800000 0x100000>;
  852.     ranges;
  853.  
  854.     ecspi1: spi@30820000 {
  855.      compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
  856.      #address-cells = <1>;
  857.      #size-cells = <0>;
  858.      reg = <0x30820000 0x10000>;
  859.      interrupts = <0 31 4>;
  860.      clocks = <&clk 159>,
  861.        <&clk 159>;
  862.      clock-names = "ipg", "per";
  863.      dmas = <&sdma1 0 7 1>, <&sdma1 1 7 2>;
  864.      dma-names = "rx", "tx";
  865.      status = "disabled";
  866.     };
  867.  
  868.     ecspi2: spi@30830000 {
  869.      compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
  870.      #address-cells = <1>;
  871.      #size-cells = <0>;
  872.      reg = <0x30830000 0x10000>;
  873.      interrupts = <0 32 4>;
  874.      clocks = <&clk 160>,
  875.        <&clk 160>;
  876.      clock-names = "ipg", "per";
  877.      dmas = <&sdma1 2 7 1>, <&sdma1 3 7 2>;
  878.      dma-names = "rx", "tx";
  879.      status = "disabled";
  880.     };
  881.  
  882.     ecspi3: spi@30840000 {
  883.      compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
  884.      #address-cells = <1>;
  885.      #size-cells = <0>;
  886.      reg = <0x30840000 0x10000>;
  887.      interrupts = <0 33 4>;
  888.      clocks = <&clk 161>,
  889.        <&clk 161>;
  890.      clock-names = "ipg", "per";
  891.      dmas = <&sdma1 4 7 1>, <&sdma1 5 7 2>;
  892.      dma-names = "rx", "tx";
  893.      status = "disabled";
  894.     };
  895.  
  896.     uart1: serial@30860000 {
  897.      compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
  898.      reg = <0x30860000 0x10000>;
  899.      interrupts = <0 26 4>;
  900.      clocks = <&clk 188>,
  901.        <&clk 188>;
  902.      clock-names = "ipg", "per";
  903.      dmas = <&sdma1 22 4 0>, <&sdma1 23 4 0>;
  904.      dma-names = "rx", "tx";
  905.      status = "disabled";
  906.     };
  907.  
  908.     uart3: serial@30880000 {
  909.      compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
  910.      reg = <0x30880000 0x10000>;
  911.      interrupts = <0 28 4>;
  912.      clocks = <&clk 190>,
  913.        <&clk 190>;
  914.      clock-names = "ipg", "per";
  915.      dmas = <&sdma1 26 4 0>, <&sdma1 27 4 0>;
  916.      dma-names = "rx", "tx";
  917.      status = "disabled";
  918.     };
  919.  
  920.     uart2: serial@30890000 {
  921.      compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
  922.      reg = <0x30890000 0x10000>;
  923.      interrupts = <0 27 4>;
  924.      clocks = <&clk 189>,
  925.        <&clk 189>;
  926.      clock-names = "ipg", "per";
  927.      status = "disabled";
  928.     };
  929.    };
  930.  
  931.    crypto: crypto@30900000 {
  932.     compatible = "fsl,sec-v4.0";
  933.     #address-cells = <1>;
  934.     #size-cells = <1>;
  935.     reg = <0x30900000 0x40000>;
  936.     ranges = <0 0x30900000 0x40000>;
  937.     interrupts = <0 91 4>;
  938.     clocks = <&clk 93>,
  939.       <&clk 95>;
  940.     clock-names = "aclk", "ipg";
  941.  
  942.     sec_jr0: jr@1000 {
  943.      compatible = "fsl,sec-v4.0-job-ring";
  944.      reg = <0x1000 0x1000>;
  945.      interrupts = <0 105 4>;
  946.     };
  947.  
  948.     sec_jr1: jr@2000 {
  949.      compatible = "fsl,sec-v4.0-job-ring";
  950.      reg = <0x2000 0x1000>;
  951.      interrupts = <0 106 4>;
  952.     };
  953.  
  954.     sec_jr2: jr@3000 {
  955.      compatible = "fsl,sec-v4.0-job-ring";
  956.      reg = <0x3000 0x1000>;
  957.      interrupts = <0 114 4>;
  958.     };
  959.    };
  960.  
  961.    i2c1: i2c@30a20000 {
  962.     compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
  963.     #address-cells = <1>;
  964.     #size-cells = <0>;
  965.     reg = <0x30a20000 0x10000>;
  966.     interrupts = <0 35 4>;
  967.     clocks = <&clk 164>;
  968.     status = "disabled";
  969.    };
  970.  
  971.    i2c2: i2c@30a30000 {
  972.     compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
  973.     #address-cells = <1>;
  974.     #size-cells = <0>;
  975.     reg = <0x30a30000 0x10000>;
  976.     interrupts = <0 36 4>;
  977.     clocks = <&clk 165>;
  978.     status = "disabled";
  979.    };
  980.  
  981.    i2c3: i2c@30a40000 {
  982.     #address-cells = <1>;
  983.     #size-cells = <0>;
  984.     compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
  985.     reg = <0x30a40000 0x10000>;
  986.     interrupts = <0 37 4>;
  987.     clocks = <&clk 166>;
  988.     status = "disabled";
  989.    };
  990.  
  991.    i2c4: i2c@30a50000 {
  992.     compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
  993.     #address-cells = <1>;
  994.     #size-cells = <0>;
  995.     reg = <0x30a50000 0x10000>;
  996.     interrupts = <0 38 4>;
  997.     clocks = <&clk 167>;
  998.     status = "disabled";
  999.    };
  1000.  
  1001.    uart4: serial@30a60000 {
  1002.     compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
  1003.     reg = <0x30a60000 0x10000>;
  1004.     interrupts = <0 29 4>;
  1005.     clocks = <&clk 191>,
  1006.       <&clk 191>;
  1007.     clock-names = "ipg", "per";
  1008.     dmas = <&sdma1 28 4 0>, <&sdma1 29 4 0>;
  1009.     dma-names = "rx", "tx";
  1010.     status = "disabled";
  1011.    };
  1012.  
  1013.    mu: mailbox@30aa0000 {
  1014.     compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
  1015.     reg = <0x30aa0000 0x10000>;
  1016.     interrupts = <0 88 4>;
  1017.     clocks = <&clk 218>;
  1018.     #mbox-cells = <2>;
  1019.    };
  1020.  
  1021.    usdhc1: mmc@30b40000 {
  1022.     compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
  1023.     reg = <0x30b40000 0x10000>;
  1024.     interrupts = <0 22 4>;
  1025.     clocks = <&clk 95>,
  1026.       <&clk 83>,
  1027.       <&clk 194>;
  1028.     clock-names = "ipg", "ahb", "per";
  1029.     fsl,tuning-start-tap = <20>;
  1030.     fsl,tuning-step= <2>;
  1031.     bus-width = <4>;
  1032.     status = "disabled";
  1033.    };
  1034.  
  1035.    usdhc2: mmc@30b50000 {
  1036.     compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
  1037.     reg = <0x30b50000 0x10000>;
  1038.     interrupts = <0 23 4>;
  1039.     clocks = <&clk 95>,
  1040.       <&clk 83>,
  1041.       <&clk 195>;
  1042.     clock-names = "ipg", "ahb", "per";
  1043.     fsl,tuning-start-tap = <20>;
  1044.     fsl,tuning-step= <2>;
  1045.     bus-width = <4>;
  1046.     status = "disabled";
  1047.    };
  1048.  
  1049.    usdhc3: mmc@30b60000 {
  1050.     compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
  1051.     reg = <0x30b60000 0x10000>;
  1052.     interrupts = <0 24 4>;
  1053.     clocks = <&clk 95>,
  1054.       <&clk 83>,
  1055.       <&clk 208>;
  1056.     clock-names = "ipg", "ahb", "per";
  1057.     fsl,tuning-start-tap = <20>;
  1058.     fsl,tuning-step= <2>;
  1059.     bus-width = <4>;
  1060.     status = "disabled";
  1061.    };
  1062.  
  1063.    flexspi: spi@30bb0000 {
  1064.     #address-cells = <1>;
  1065.     #size-cells = <0>;
  1066.     compatible = "nxp,imx8mm-fspi";
  1067.     reg = <0x30bb0000 0x10000>, <0x8000000 0x10000000>;
  1068.     reg-names = "fspi_base", "fspi_mmap";
  1069.     interrupts = <0 107 4>;
  1070.     clocks = <&clk 174>,
  1071.       <&clk 174>;
  1072.     clock-names = "fspi_en", "fspi";
  1073.     status = "disabled";
  1074.    };
  1075.  
  1076.    sdma1: dma-controller@30bd0000 {
  1077.     compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
  1078.     reg = <0x30bd0000 0x10000>;
  1079.     interrupts = <0 2 4>;
  1080.     clocks = <&clk 211>,
  1081.       <&clk 93>;
  1082.     clock-names = "ipg", "ahb";
  1083.     #dma-cells = <3>;
  1084.     fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
  1085.    };
  1086.  
  1087.    fec1: ethernet@30be0000 {
  1088.     compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
  1089.     reg = <0x30be0000 0x10000>;
  1090.     interrupts = <0 118 4>,
  1091.           <0 119 4>,
  1092.           <0 120 4>,
  1093.           <0 121 4>;
  1094.     clocks = <&clk 162>,
  1095.       <&clk 162>,
  1096.       <&clk 117>,
  1097.       <&clk 116>,
  1098.       <&clk 118>;
  1099.     clock-names = "ipg", "ahb", "ptp",
  1100.            "enet_clk_ref", "enet_out";
  1101.     assigned-clocks = <&clk 82>,
  1102.         <&clk 117>,
  1103.         <&clk 116>,
  1104.         <&clk 118>;
  1105.     assigned-clock-parents = <&clk 54>,
  1106.         <&clk 58>,
  1107.         <&clk 59>,
  1108.         <&clk 57>;
  1109.     assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
  1110.     fsl,num-tx-queues = <3>;
  1111.     fsl,num-rx-queues = <3>;
  1112.     nvmem-cells = <&fec_mac_address>;
  1113.     nvmem-cell-names = "mac-address";
  1114.     fsl,stop-mode = <&gpr 0x10 3>;
  1115.     status = "disabled";
  1116.    };
  1117.  
  1118.   };
  1119.  
  1120.   aips4: bus@32c00000 {
  1121.    compatible = "fsl,aips-bus", "simple-bus";
  1122.    reg = <0x32c00000 0x400000>;
  1123.    #address-cells = <1>;
  1124.    #size-cells = <1>;
  1125.    ranges = <0x32c00000 0x32c00000 0x400000>;
  1126.  
  1127.    csi: csi@32e20000 {
  1128.     compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
  1129.     reg = <0x32e20000 0x1000>;
  1130.     interrupts = <0 16 4>;
  1131.     clocks = <&clk 219>;
  1132.     clock-names = "mclk";
  1133.     power-domains = <&disp_blk_ctrl 0>;
  1134.     status = "disabled";
  1135.  
  1136.     port {
  1137.      csi_in: endpoint {
  1138.       remote-endpoint = <&imx8mm_mipi_csi_out>;
  1139.      };
  1140.     };
  1141.    };
  1142.  
  1143.    disp_blk_ctrl: blk-ctrl@32e28000 {
  1144.     compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
  1145.     reg = <0x32e28000 0x100>;
  1146.     power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
  1147.       <&pgc_dispmix>, <&pgc_mipi>,
  1148.       <&pgc_mipi>;
  1149.     power-domain-names = "bus", "csi-bridge",
  1150.            "lcdif", "mipi-dsi",
  1151.            "mipi-csi";
  1152.     clocks = <&clk 205>,
  1153.       <&clk 206>,
  1154.       <&clk 219>,
  1155.       <&clk 205>,
  1156.       <&clk 206>,
  1157.       <&clk 204>,
  1158.       <&clk 142>,
  1159.       <&clk 143>,
  1160.       <&clk 146>,
  1161.       <&clk 147>;
  1162.     clock-names = "csi-bridge-axi","csi-bridge-apb",
  1163.            "csi-bridge-core", "lcdif-axi",
  1164.            "lcdif-apb", "lcdif-pix",
  1165.            "dsi-pclk", "dsi-ref",
  1166.            "csi-aclk", "csi-pclk";
  1167.     #power-domain-cells = <1>;
  1168.    };
  1169.  
  1170.    mipi_csi: mipi-csi@32e30000 {
  1171.     compatible = "fsl,imx8mm-mipi-csi2";
  1172.     reg = <0x32e30000 0x1000>;
  1173.     interrupts = <0 17 4>;
  1174.     assigned-clocks = <&clk 146>,
  1175.         <&clk 147>;
  1176.     assigned-clock-parents = <&clk 65>,
  1177.          <&clk 65>;
  1178.     clock-frequency = <333000000>;
  1179.     clocks = <&clk 206>,
  1180.       <&clk 219>,
  1181.       <&clk 147>,
  1182.       <&clk 205>;
  1183.     clock-names = "pclk", "wrap", "phy", "axi";
  1184.     power-domains = <&disp_blk_ctrl 3>;
  1185.     status = "disabled";
  1186.  
  1187.     ports {
  1188.      #address-cells = <1>;
  1189.      #size-cells = <0>;
  1190.  
  1191.      port@0 {
  1192.       reg = <0>;
  1193.      };
  1194.  
  1195.      port@1 {
  1196.       reg = <1>;
  1197.  
  1198.       imx8mm_mipi_csi_out: endpoint {
  1199.        remote-endpoint = <&csi_in>;
  1200.       };
  1201.      };
  1202.     };
  1203.    };
  1204.  
  1205.    lcdif: lcdif@32e00000 {
  1206.     compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
  1207.     reg = <0x32e00000 0x10000>;
  1208.     clocks = <&clk 107>,
  1209.       <&clk 205>,
  1210.       <&clk 206>;
  1211.     clock-names = "pix", "disp_axi", "axi";
  1212.     assigned-clocks = <&clk 107>,
  1213.         <&clk 85>,
  1214.         <&clk 86>;
  1215.     assigned-clock-parents = <&clk 40>,
  1216.         <&clk 65>,
  1217.         <&clk 56>;
  1218.     assigned-clock-rate = <594000000>, <500000000>, <200000000>;
  1219.     interrupts = <0 5 4>;
  1220.     power-domains = <&dispmix_blk_ctl 1>;
  1221.     status = "disabled";
  1222.  
  1223.     port {
  1224.      lcdif_out_dsi: endpoint {
  1225.       remote-endpoint = <&dsi_in_lcdif>;
  1226.      };
  1227.     };
  1228.    };
  1229.  
  1230.    dsi: dsi@32e10000 {
  1231.     compatible = "fsl,imx8mm-sec-dsim";
  1232.     reg = <0x32e10000 0xa0>;
  1233.     clocks = <&clk 142>,
  1234.       <&clk 143>;
  1235.     clock-names = "bus", "phy_ref";
  1236.     assigned-clocks = <&clk 142>,
  1237.         <&clk 40>,
  1238.         <&clk 143>;
  1239.     assigned-clock-parents = <&clk 54>,
  1240.         <&clk 30>,
  1241.         <&clk 40>;
  1242.     assigned-clock-rates = <266000000>, <594000000>, <27000000>;
  1243.     interrupts = <0 18 4>;
  1244.     phys = <&dphy>;
  1245.     phy-names = "dphy";
  1246.     power-domains = <&dispmix_blk_ctl 2>;
  1247.     samsung,burst-clock-frequency = <891000000>;
  1248.     samsung,esc-clock-frequency = <54000000>;
  1249.     samsung,pll-clock-frequency = <27000000>;
  1250.     status = "disabled";
  1251.  
  1252.     ports {
  1253.      #address-cells = <1>;
  1254.      #size-cells = <0>;
  1255.  
  1256.      port@0 {
  1257.       reg = <0>;
  1258.       #address-cells = <1>;
  1259.       #size-cells = <0>;
  1260.  
  1261.       dsi_in_lcdif: endpoint@0 {
  1262.        reg = <0>;
  1263.        remote-endpoint = <&lcdif_out_dsi>;
  1264.       };
  1265.      };
  1266.  
  1267.      port@1 {
  1268.       reg = <1>;
  1269.      };
  1270.     };
  1271.    };
  1272.  
  1273.    dphy: dphy@32e100a4 {
  1274.     compatible = "fsl,imx8mm-sec-dsim-dphy";
  1275.     reg = <0x32e100a4 0xbc>;
  1276.     clocks = <&clk 143>;
  1277.     clock-names = "phy_ref";
  1278.     #phy-cells = <0>;
  1279.     power-domains = <&dispmix_blk_ctl 4>;
  1280.     status = "disabled";
  1281.    };
  1282.  
  1283.    dispmix_blk_ctl: blk-ctl@32e28000 {
  1284.     compatible = "fsl,imx8mm-dispmix-blk-ctl", "syscon";
  1285.     reg = <0x32e28000 0x100>;
  1286.     #power-domain-cells = <1>;
  1287.     power-domains = <&pgc_dispmix>, <&pgc_mipi>;
  1288.     power-domain-names = "dispmix", "mipi";
  1289.     clocks = <&clk 204>,
  1290.       <&clk 205>,
  1291.       <&clk 206>;
  1292.     clock-names = "disp", "axi", "apb";
  1293.    };
  1294.  
  1295.    usbotg1: usb@32e40000 {
  1296.     compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
  1297.     reg = <0x32e40000 0x200>;
  1298.     interrupts = <0 40 4>;
  1299.     clocks = <&clk 192>;
  1300.     clock-names = "usb1_ctrl_root_clk";
  1301.     assigned-clocks = <&clk 88>;
  1302.     assigned-clock-parents = <&clk 64>;
  1303.     phys = <&usbphynop1>;
  1304.     fsl,usbmisc = <&usbmisc1 0>;
  1305.     power-domains = <&pgc_otg1>;
  1306.     status = "disabled";
  1307.    };
  1308.  
  1309.    usbmisc1: usbmisc@32e40200 {
  1310.     compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
  1311.     #index-cells = <1>;
  1312.     reg = <0x32e40200 0x200>;
  1313.    };
  1314.  
  1315.    usbotg2: usb@32e50000 {
  1316.     compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb";
  1317.     reg = <0x32e50000 0x200>;
  1318.     interrupts = <0 41 4>;
  1319.     clocks = <&clk 192>;
  1320.     clock-names = "usb1_ctrl_root_clk";
  1321.     assigned-clocks = <&clk 88>;
  1322.     assigned-clock-parents = <&clk 64>;
  1323.     phys = <&usbphynop2>;
  1324.     fsl,usbmisc = <&usbmisc2 0>;
  1325.     power-domains = <&pgc_otg2>;
  1326.     status = "disabled";
  1327.    };
  1328.  
  1329.    usbmisc2: usbmisc@32e50200 {
  1330.     compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc";
  1331.     #index-cells = <1>;
  1332.     reg = <0x32e50200 0x200>;
  1333.    };
  1334.  
  1335.    pcie_phy: pcie-phy@32f00000 {
  1336.     compatible = "fsl,imx8mm-pcie-phy";
  1337.     reg = <0x32f00000 0x10000>;
  1338.     clocks = <&clk 104>;
  1339.     clock-names = "ref";
  1340.     assigned-clocks = <&clk 104>;
  1341.     assigned-clock-rates = <100000000>;
  1342.     assigned-clock-parents = <&clk 58>;
  1343.     resets = <&src 26>;
  1344.     reset-names = "pciephy";
  1345.     #phy-cells = <0>;
  1346.     status = "disabled";
  1347.    };
  1348.   };
  1349.  
  1350.   dma_apbh: dma-controller@33000000 {
  1351.    compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
  1352.    reg = <0x33000000 0x2000>;
  1353.    interrupts = <0 12 4>,
  1354.          <0 12 4>,
  1355.          <0 12 4>,
  1356.          <0 12 4>;
  1357.    interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
  1358.    #dma-cells = <1>;
  1359.    dma-channels = <4>;
  1360.    clocks = <&clk 222>;
  1361.   };
  1362.  
  1363.   gpmi: nand-controller@33002000{
  1364.    compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
  1365.    #address-cells = <1>;
  1366.    #size-cells = <1>;
  1367.    reg = <0x33002000 0x2000>, <0x33004000 0x4000>;
  1368.    reg-names = "gpmi-nand", "bch";
  1369.    interrupts = <0 14 4>;
  1370.    interrupt-names = "bch";
  1371.    clocks = <&clk 175>,
  1372.      <&clk 222>;
  1373.    clock-names = "gpmi_io", "gpmi_bch_apb";
  1374.    dmas = <&dma_apbh 0>;
  1375.    dma-names = "rx-tx";
  1376.    status = "disabled";
  1377.   };
  1378.  
  1379.   pcie0: pcie@33800000 {
  1380.    compatible = "fsl,imx8mm-pcie";
  1381.    reg = <0x33800000 0x400000>, <0x1ff00000 0x80000>;
  1382.    reg-names = "dbi", "config";
  1383.    #address-cells = <3>;
  1384.    #size-cells = <2>;
  1385.    device_type = "pci";
  1386.    bus-range = <0x00 0xff>;
  1387.    ranges = <0x81000000 0 0x00000000 0x1ff80000 0 0x00010000
  1388.        0x82000000 0 0x18000000 0x18000000 0 0x07f00000>;
  1389.    num-lanes = <1>;
  1390.    num-viewport = <4>;
  1391.    interrupts = <0 122 4>;
  1392.    interrupt-names = "msi";
  1393.    #interrupt-cells = <1>;
  1394.    interrupt-map-mask = <0 0 0 0x7>;
  1395.    interrupt-map = <0 0 0 1 &gic 0 125 4>,
  1396.      <0 0 0 2 &gic 0 124 4>,
  1397.      <0 0 0 3 &gic 0 123 4>,
  1398.      <0 0 0 4 &gic 0 122 4>;
  1399.    fsl,max-link-speed = <2>;
  1400.    linux,pci-domain = <0>;
  1401.    power-domains = <&pgc_pcie>;
  1402.    resets = <&src 28>,
  1403.      <&src 29>;
  1404.    reset-names = "apps", "turnoff";
  1405.    phys = <&pcie_phy>;
  1406.    phy-names = "pcie-phy";
  1407.    status = "disabled";
  1408.   };
  1409.  
  1410.   gpu_3d: gpu@38000000 {
  1411.    compatible = "vivante,gc";
  1412.    reg = <0x38000000 0x8000>;
  1413.    interrupts = <0 3 4>;
  1414.    clocks = <&clk 90>,
  1415.      <&clk 200>,
  1416.      <&clk 193>,
  1417.      <&clk 193>;
  1418.    clock-names = "reg", "bus", "core", "shader";
  1419.    assigned-clocks = <&clk 248>,
  1420.        <&clk 42>;
  1421.    assigned-clock-parents = <&clk 42>;
  1422.    assigned-clock-rates = <0>, <1000000000>;
  1423.    power-domains = <&pgc_gpu>;
  1424.   };
  1425.  
  1426.   gpu_2d: gpu@38008000 {
  1427.    compatible = "vivante,gc";
  1428.    reg = <0x38008000 0x8000>;
  1429.    interrupts = <0 25 4>;
  1430.    clocks = <&clk 90>,
  1431.      <&clk 200>,
  1432.      <&clk 217>;
  1433.    clock-names = "reg", "bus", "core";
  1434.    assigned-clocks = <&clk 249>,
  1435.        <&clk 42>;
  1436.    assigned-clock-parents = <&clk 42>;
  1437.    assigned-clock-rates = <0>, <1000000000>;
  1438.    power-domains = <&pgc_gpu>;
  1439.   };
  1440.  
  1441.   vpu_g1: video-codec@38300000 {
  1442.    compatible = "nxp,imx8mm-vpu-g1";
  1443.    reg = <0x38300000 0x10000>;
  1444.    interrupts = <0 7 4>;
  1445.    clocks = <&clk 199>;
  1446.    power-domains = <&vpu_blk_ctrl 0>;
  1447.   };
  1448.  
  1449.   vpu_g2: video-codec@38310000 {
  1450.    compatible = "nxp,imx8mq-vpu-g2";
  1451.    reg = <0x38310000 0x10000>;
  1452.    interrupts = <0 8 4>;
  1453.    clocks = <&clk 202>;
  1454.    power-domains = <&vpu_blk_ctrl 1>;
  1455.   };
  1456.  
  1457.   vpu_blk_ctrl: blk-ctrl@38330000 {
  1458.    compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
  1459.    reg = <0x38330000 0x100>;
  1460.    power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
  1461.      <&pgc_vpu_g2>, <&pgc_vpu_h1>;
  1462.    power-domain-names = "bus", "g1", "g2", "h1";
  1463.    clocks = <&clk 199>,
  1464.      <&clk 202>,
  1465.      <&clk 201>;
  1466.    clock-names = "g1", "g2", "h1";
  1467.    assigned-clocks = <&clk 99>,
  1468.        <&clk 100>;
  1469.    assigned-clock-parents = <&clk 43>,
  1470.        <&clk 43>;
  1471.    assigned-clock-rates = <600000000>,
  1472.             <600000000>;
  1473.    #power-domain-cells = <1>;
  1474.   };
  1475.  
  1476.   gic: interrupt-controller@38800000 {
  1477.    compatible = "arm,gic-v3";
  1478.    reg = <0x38800000 0x10000>,
  1479.          <0x38880000 0xc0000>;
  1480.    #interrupt-cells = <3>;
  1481.    interrupt-controller;
  1482.    interrupts = <1 9 4>;
  1483.   };
  1484.  
  1485.   ddrc: memory-controller@3d400000 {
  1486.    compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
  1487.    reg = <0x3d400000 0x400000>;
  1488.    clock-names = "core", "pll", "alt", "apb";
  1489.    clocks = <&clk 220>,
  1490.      <&clk 21>,
  1491.      <&clk 97>,
  1492.      <&clk 98>;
  1493.   };
  1494.  
  1495.   ddr-pmu@3d800000 {
  1496.    compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";
  1497.    reg = <0x3d800000 0x400000>;
  1498.    interrupts = <0 98 4>;
  1499.   };
  1500.  };
  1501. };
  1502. # 16 "arch/arm64/boot/dts/msc/imx8mm/msc-imx8mm.dtsi" 2
  1503.  
  1504. &aips4 {
  1505. # 44 "arch/arm64/boot/dts/msc/imx8mm/msc-imx8mm.dtsi"
  1506.                         csi1_bridge: csi1_bridge@32e20000 {
  1507.                                 compatible = "fsl,imx8mm-csi", "fsl,imx8mq-csi", "fsl,imx6s-csi";
  1508.                                 reg = <0x32e20000 0x1000>;
  1509.                                 interrupts = <0 16 4>;
  1510.                                 clocks = <&clk 205>,
  1511.                                         <&clk 219>,
  1512.                                         <&clk 206>;
  1513.                                 clock-names = "disp-axi", "csi_mclk", "disp_dcic";
  1514.                                 power-domains = <&dispmix_pd>;
  1515.                                 status = "disabled";
  1516.                         };
  1517.  
  1518.                         mipi_csi_1: mipi_csi@32e30000 {
  1519.                                 compatible = "fsl,imx8mm-mipi-csi";
  1520.                                 reg = <0x32e30000 0x1000>;
  1521.                                 interrupts = <0 17 4>;
  1522.                                 clock-frequency = <333000000>;
  1523.                                 clocks = <&clk 146>,
  1524.                                         <&clk 147>,
  1525.                                         <&clk 205>,
  1526.                                         <&clk 206>;
  1527.                                 clock-names = "mipi_clk", "phy_clk", "disp_axi", "disp_apb";
  1528.                                 bus-width = <4>;
  1529.                                 power-domains = <&mipi_pd>;
  1530.                                 status = "disabled";
  1531.                         };
  1532.  
  1533.                         dispmix_gpr: display-gpr@32e28000 {
  1534.                                 compatible = "fsl, imx8mm-iomuxc-gpr", "syscon";
  1535.                                 reg = <0x32e28000 0x100>;
  1536.                         };
  1537.  
  1538.  
  1539. };
  1540.  
  1541. / {
  1542.  aliases {
  1543.   gpu = &gpu_3d;
  1544.  };
  1545.         power_domains {
  1546.  
  1547.                 dispmix_pd: dispmix-pd {
  1548.                         compatible = "fsl,imx8m-pm-domain";
  1549.                         #power-domain-cells = <0>;
  1550.                         domain-index = <9>;
  1551.                         domain-name = "dispmix";
  1552.                         clocks = <&clk 204>,
  1553.                                  <&clk 205>,
  1554.                                  <&clk 206>;
  1555.                 };
  1556.  
  1557.                 mipi_pd: mipi-pd {
  1558.                         compatible = "fsl,imx8m-pm-domain";
  1559.                         #power-domain-cells = <0>;
  1560.                         domain-index = <10>;
  1561.                         domain-name = "mipi";
  1562.                         parent-domains = <&dispmix_pd>;
  1563.                 };
  1564.  
  1565.                 vpu_h1_pd: vpuh1-pd {
  1566.                         compatible = "fsl,imx8m-pm-domain";
  1567.                         #power-domain-cells = <0>;
  1568.                         domain-index = <8>;
  1569.                         domain-name = "vpu_h1";
  1570.                         parent-domains = <&vpumix_pd>;
  1571.                         clocks = <&clk 201>;
  1572.                 };
  1573.  
  1574.  
  1575.                 vpumix_pd: vpumix-pd {
  1576.                         compatible = "fsl,imx8m-pm-domain";
  1577.                         #power-domain-cells = <0>;
  1578.                         domain-index = <5>;
  1579.                         domain-name = "vpumix";
  1580.                         clocks = <&clk 210>;
  1581.                 };
  1582.  
  1583.         };
  1584.  
  1585.         dispmix-reset {
  1586.                 compatible = "simple-bus";
  1587.                 #address-cells = <2>;
  1588.                 #size-cells = <2>;
  1589.                 ranges;
  1590.  
  1591.                 dispmix_sft_rstn: dispmix-sft-rstn@32e28000 {
  1592.                         compatible = "fsl,imx8mm-dispmix-sft-rstn";
  1593.                         reg = <0x0 0x32e28000 0x0 0x4>;
  1594.                         clocks = <&clk 206>;
  1595.                         clock-names = "disp_apb_root_clk";
  1596.                         active_low;
  1597.                         power-domains = <&dispmix_pd>;
  1598.                         #reset-cells = <1>;
  1599.                 };
  1600.  
  1601.                 dispmix_clk_en: dispmix-clk-en@32e28004 {
  1602.                         compatible = "fsl,imx8mm-dispmix-clk-en";
  1603.                         reg = <0x0 0x32e28004 0x0 0x4>;
  1604.                         clocks = <&clk 206>;
  1605.                         clock-names = "disp_apb_root_clk";
  1606.                         power-domains = <&dispmix_pd>;
  1607.                         #reset-cells = <1>;
  1608.                 };
  1609.  
  1610.                 dispmix_mipi_rst: dispmix-mipi-rst@32e28008 {
  1611.                         compatible = "fsl,imx8mm-dispmix-mipi-rst";
  1612.                         reg = <0x0 0x32e28008 0x0 0x4>;
  1613.                         clocks = <&clk 206>;
  1614.                         clock-names = "disp_apb_root_clk";
  1615.                         active_low;
  1616.                         power-domains = <&dispmix_pd>;
  1617.                         #reset-cells = <1>;
  1618.                 };
  1619.         };
  1620.  
  1621.         mipi_dsi_resets: mipi-dsi-resets {
  1622.                 #address-cells = <1>;
  1623.                 #size-cells = <0>;
  1624.                 #reset-cells = <0>;
  1625.  
  1626.                 dsi-soft-resetn {
  1627.                         compatible = "dsi,soft-resetn";
  1628.                         resets = <&dispmix_sft_rstn 5>;
  1629.                 };
  1630.  
  1631.                 dsi-clk-enable {
  1632.                         compatible = "dsi,clk-enable";
  1633.                         resets = <&dispmix_clk_en 9>,
  1634.                                  <&dispmix_clk_en 8>;
  1635.                 };
  1636.  
  1637.                 dsi-mipi-reset {
  1638.                         compatible = "dsi,mipi-reset";
  1639.                         resets = <&dispmix_mipi_rst 1>;
  1640.                 };
  1641.         };
  1642.  
  1643.         vpu_h1: vpu_h1@38320000 {
  1644.                 compatible = "nxp,imx8mm-hantro-h1";
  1645.                 reg = <0x0 0x38320000 0x0 0x10000>;
  1646.                 reg-names = "regs_hantro_h1";
  1647.                 interrupts = <0 30 4>;
  1648.                 interrupt-names = "irq_hantro_h1";
  1649.                 clocks = <&clk 201>, <&clk 210>;
  1650.                 clock-names = "clk_hantro_h1", "clk_hantro_h1_bus";
  1651.                 assigned-clocks = <&clk 157>,<&clk 84>;
  1652.                 assigned-clock-parents = <&clk 43>, <&clk 56>;
  1653.                 assigned-clock-rates = <600000000>, <800000000>;
  1654.                 power-domains = <&vpu_h1_pd>;
  1655.                 status = "disabled";
  1656.         };
  1657.  
  1658. };
  1659. # 17 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-base.dtsi" 2
  1660. # 1 "./scripts/dtc/include-prefixes/dt-bindings/net/ti-dp83867.h" 1
  1661. # 18 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-base.dtsi" 2
  1662. # 1 "./scripts/dtc/include-prefixes/dt-bindings/input/snvs_pwrkey.h" 1
  1663. # 19 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-base.dtsi" 2
  1664.  
  1665. &iomuxc {
  1666.  
  1667.  pinctrl-names = "default";
  1668.  pinctrl-0 = <&pinctrl_hog>, <&pinctrl_smarc_gpio>;
  1669.  
  1670.  sm2s-imx8mm {
  1671.  
  1672.   pinctrl_smarc_gpio: smarcgrp-gpio {
  1673.    fsl,pins = <
  1674.  
  1675.     0x028 0x290 0x000 0x0 0x0 0x40000019
  1676.  
  1677.     0x02C 0x294 0x000 0x0 0x0 0x40000019
  1678.  
  1679.     0x034 0x29C 0x000 0x0 0x0 0x40000019
  1680.  
  1681.     0x03C 0x2A4 0x000 0x0 0x0 0x19
  1682.  
  1683.     0x040 0x2A8 0x000 0x0 0x0 0x40000019
  1684.  
  1685.     0x1E4 0x44C 0x000 0x5 0x0 0x40000019
  1686.  
  1687.     0x1E0 0x448 0x000 0x5 0x0 0x40000019
  1688.  
  1689.     0x1B4 0x41C 0x000 0x5 0x0 0x40000019
  1690.  
  1691.     0x158 0x3C0 0x000 0x5 0x0 0x40000019
  1692.  
  1693.     0x1CC 0x434 0x000 0x5 0x0 0x40000019
  1694.  
  1695.     0x04C 0x2B4 0x000 0x0 0x0 0x40000019
  1696.  
  1697.     0x044 0x2AC 0x000 0x0 0x0 0x40000019
  1698.    >;
  1699.   };
  1700.  
  1701.   pinctrl_hog: hoggrp {
  1702.    fsl,pins = <
  1703.  
  1704.     0x140 0x3A8 0x000 0x5 0x0 0x19
  1705.  
  1706.     0x144 0x3AC 0x000 0x5 0x0 0x19
  1707.  
  1708.     0x178 0x3E0 0x000 0x5 0x0 0x19
  1709.  
  1710.     0x1E8 0x450 0x000 0x5 0x0 0x19
  1711.  
  1712.     0x1C8 0x430 0x000 0x5 0x0 0x19
  1713.  
  1714.     0x1AC 0x414 0x000 0x5 0x0 0x40000019
  1715.  
  1716.     0x180 0x3E8 0x000 0x5 0x0 0x40000019
  1717.  
  1718.     0x1A8 0x410 0x000 0x5 0x0 0x40000019
  1719.  
  1720.     0x1A4 0x40C 0x000 0x5 0x0 0x40000019
  1721.  
  1722.     0x1A0 0x408 0x000 0x5 0x0 0x40000019
  1723.    >;
  1724.   };
  1725.  
  1726.   pinctrl_fec1: fec1grp {
  1727.    fsl,pins = <
  1728.  
  1729.     0x068 0x2D0 0x000 0x0 0x0 0x3
  1730.  
  1731.     0x06C 0x2D4 0x4C0 0x0 0x1 0x3
  1732.  
  1733.     0x080 0x2E8 0x000 0x0 0x0 0x1f
  1734.  
  1735.     0x084 0x2EC 0x000 0x0 0x0 0x1f
  1736.  
  1737.     0x07C 0x2E4 0x000 0x0 0x0 0x1f
  1738.  
  1739.     0x078 0x2E0 0x000 0x0 0x0 0x1f
  1740.  
  1741.     0x074 0x2DC 0x000 0x0 0x0 0x1f
  1742.  
  1743.     0x070 0x2D8 0x000 0x0 0x0 0x1f
  1744.  
  1745.     0x088 0x2F0 0x000 0x0 0x0 0x91
  1746.  
  1747.     0x08C 0x2F4 0x000 0x0 0x0 0x91
  1748.  
  1749.     0x090 0x2F8 0x000 0x0 0x0 0x91
  1750.  
  1751.     0x094 0x2FC 0x000 0x0 0x0 0x91
  1752.  
  1753.     0x098 0x300 0x000 0x0 0x0 0x91
  1754.  
  1755.     0x09C 0x304 0x000 0x0 0x0 0x91
  1756.  
  1757.     0x0FC 0x364 0x000 0x5 0x0 0x19
  1758.  
  1759.     0x100 0x368 0x000 0x5 0x0 0x40000019
  1760.  
  1761.     0x048 0x2B0 0x000 0x1 0x0 0x19
  1762.    >;
  1763.   };
  1764.  
  1765.  
  1766.   pinctrl_i2c1: i2c1grp {
  1767.    fsl,pins = <
  1768.  
  1769.     0x214 0x47C 0x000 0x0 0x0 0x400001c3
  1770.  
  1771.     0x218 0x480 0x000 0x0 0x0 0x400001c3
  1772.    >;
  1773.  
  1774.   };
  1775.  
  1776.  
  1777.   pinctrl_i2c2: i2c2grp {
  1778.    fsl,pins = <
  1779.  
  1780.     0x21C 0x484 0x000 0x0 0x0 0x400001c3
  1781.  
  1782.     0x220 0x488 0x000 0x0 0x0 0x400001c3
  1783.    >;
  1784.   };
  1785.  
  1786.  
  1787.   pinctrl_i2c3: i2c3grp {
  1788.    fsl,pins = <
  1789.  
  1790.     0x224 0x48C 0x000 0x0 0x0 0x400001c3
  1791.  
  1792.     0x228 0x490 0x000 0x0 0x0 0x400001c3
  1793.    >;
  1794.   };
  1795.  
  1796.  
  1797.   pinctrl_i2c4: i2c4grp {
  1798.    fsl,pins = <
  1799.  
  1800.     0x22C 0x494 0x000 0x0 0x0 0x400001c3
  1801.  
  1802.     0x230 0x498 0x000 0x0 0x0 0x400001c3
  1803.    >;
  1804.   };
  1805.  
  1806.  
  1807.   pinctrl_i2c_cam: i2ccamgrp {
  1808.    fsl,pins = <
  1809.  
  1810.     0x23C 0x4A4 0x000 0x5 0x0 0x4000016
  1811.  
  1812.     0x240 0x4A8 0x000 0x5 0x0 0x4000016
  1813.    >;
  1814.   };
  1815.  
  1816.  
  1817.   pinctrl_uart1: uart1grp {
  1818.    fsl,pins = <
  1819.  
  1820.     0x234 0x49C 0x4F4 0x0 0x0 0x49
  1821.  
  1822.     0x238 0x4A0 0x000 0x0 0x0 0x49
  1823.  
  1824.     0x1BC 0x424 0x000 0x5 0x0 0x116
  1825.  
  1826.     0x1B8 0x420 0x000 0x5 0x0 0x116
  1827.    >;
  1828.   };
  1829.  
  1830.  
  1831.   pinctrl_uart2: uart2grp {
  1832.    fsl,pins = <
  1833.  
  1834.     0x1D8 0x440 0x4FC 0x4 0x2 0x49
  1835.  
  1836.     0x1DC 0x444 0x000 0x4 0x0 0x49
  1837.  
  1838.     0x1D4 0x43C 0x000 0x5 0x0 0x116
  1839.  
  1840.     0x1D0 0x438 0x000 0x5 0x0 0x116
  1841.    >;
  1842.   };
  1843.  
  1844.  
  1845.   pinctrl_uart3: uart3grp {
  1846.    fsl,pins = <
  1847.  
  1848.     0x244 0x4AC 0x504 0x0 0x2 0x49
  1849.  
  1850.     0x248 0x4B0 0x000 0x0 0x0 0x49
  1851.    >;
  1852.   };
  1853.  
  1854.  
  1855.   pinctrl_uart4: uart4grp {
  1856.    fsl,pins = <
  1857.  
  1858.     0x24C 0x4B4 0x50C 0x0 0x2 0x49
  1859.  
  1860.     0x250 0x4B8 0x000 0x0 0x0 0x49
  1861.    >;
  1862.   };
  1863.  
  1864.   pinctrl_usdhc1_reset: usdhc1grp-reset {
  1865.    fsl,pins = <
  1866.  
  1867.     0x0C8 0x330 0x000 0x0 0x0 0x116
  1868.    >;
  1869.   };
  1870.  
  1871.   pinctrl_usdhc1: usdhc1grp {
  1872.    fsl,pins = <
  1873.  
  1874.     0x0A0 0x308 0x000 0x0 0x0 0x40000190
  1875.  
  1876.     0x0A4 0x30C 0x000 0x0 0x0 0x1d0
  1877.  
  1878.     0x0A8 0x310 0x000 0x0 0x0 0x1d0
  1879.  
  1880.     0x0AC 0x314 0x000 0x0 0x0 0x1d0
  1881.  
  1882.     0x0B0 0x318 0x000 0x0 0x0 0x1d0
  1883.  
  1884.     0x0B4 0x31C 0x000 0x0 0x0 0x1d0
  1885.  
  1886.     0x0B8 0x320 0x000 0x0 0x0 0x1d0
  1887.  
  1888.     0x0BC 0x324 0x000 0x0 0x0 0x1d0
  1889.  
  1890.     0x0C0 0x328 0x000 0x0 0x0 0x1d0
  1891.  
  1892.     0x0C4 0x32C 0x000 0x0 0x0 0x1d0
  1893.  
  1894.     0x0CC 0x334 0x000 0x0 0x0 0x190
  1895.    >;
  1896.   };
  1897.  
  1898.   pinctrl_usdhc1_100mhz: usdhc1grp-100mhz {
  1899.    fsl,pins = <
  1900.  
  1901.     0x0A0 0x308 0x000 0x0 0x0 0x40000194
  1902.  
  1903.     0x0A4 0x30C 0x000 0x0 0x0 0x1d4
  1904.  
  1905.     0x0A8 0x310 0x000 0x0 0x0 0x1d4
  1906.  
  1907.     0x0AC 0x314 0x000 0x0 0x0 0x1d4
  1908.  
  1909.     0x0B0 0x318 0x000 0x0 0x0 0x1d4
  1910.  
  1911.     0x0B4 0x31C 0x000 0x0 0x0 0x1d4
  1912.  
  1913.     0x0B8 0x320 0x000 0x0 0x0 0x1d4
  1914.  
  1915.     0x0BC 0x324 0x000 0x0 0x0 0x1d4
  1916.  
  1917.     0x0C0 0x328 0x000 0x0 0x0 0x1d4
  1918.  
  1919.     0x0C4 0x32C 0x000 0x0 0x0 0x1d4
  1920.  
  1921.     0x0CC 0x334 0x000 0x0 0x0 0x194
  1922.    >;
  1923.   };
  1924.  
  1925.   pinctrl_usdhc1_200mhz: usdhc1grp-200mhz {
  1926.    fsl,pins = <
  1927.  
  1928.     0x0A0 0x308 0x000 0x0 0x0 0x40000196
  1929.  
  1930.     0x0A4 0x30C 0x000 0x0 0x0 0x1d6
  1931.  
  1932.     0x0A8 0x310 0x000 0x0 0x0 0x1d6
  1933.  
  1934.     0x0AC 0x314 0x000 0x0 0x0 0x1d6
  1935.  
  1936.     0x0B0 0x318 0x000 0x0 0x0 0x1d6
  1937.  
  1938.     0x0B4 0x31C 0x000 0x0 0x0 0x1d6
  1939.  
  1940.     0x0B8 0x320 0x000 0x0 0x0 0x1d6
  1941.  
  1942.     0x0BC 0x324 0x000 0x0 0x0 0x1d6
  1943.  
  1944.     0x0C0 0x328 0x000 0x0 0x0 0x1d6
  1945.  
  1946.     0x0C4 0x32C 0x000 0x0 0x0 0x1d6
  1947.  
  1948.     0x0CC 0x334 0x000 0x0 0x0 0x196
  1949.    >;
  1950.   };
  1951.  
  1952.   pinctrl_usdhc2_gpio: usdhc2grp-gpio {
  1953.    fsl,pins = <
  1954.  
  1955.     0x0EC 0x354 0x000 0x5 0x0 0x36
  1956.  
  1957.     0x0D0 0x338 0x000 0x5 0x0 0x41
  1958.  
  1959.     0x0F0 0x358 0x000 0x5 0x0 0x41
  1960.  
  1961.     0x12C 0x394 0x000 0x5 0x0 0x41
  1962.  
  1963.     0x038 0x2A0 0x000 0x1 0x0 0x1d0
  1964.    >;
  1965.   };
  1966.  
  1967.   pinctrl_usdhc2: usdhc2grp {
  1968.    fsl,pins = <
  1969.  
  1970.     0x0D4 0x33C 0x000 0x0 0x0 0x92
  1971.  
  1972.     0x0D8 0x340 0x000 0x0 0x0 0x92
  1973.  
  1974.     0x0DC 0x344 0x000 0x0 0x0 0x92
  1975.  
  1976.     0x0E0 0x348 0x000 0x0 0x0 0x92
  1977.  
  1978.     0x0E4 0x34C 0x000 0x0 0x0 0x92
  1979.  
  1980.     0x0E8 0x350 0x000 0x0 0x0 0x92
  1981.    >;
  1982.   };
  1983.  
  1984.   pinctrl_usdhc2_100mhz: usdhc2grp-100mhz {
  1985.    fsl,pins = <
  1986.  
  1987.     0x0D4 0x33C 0x000 0x0 0x0 0x94
  1988.  
  1989.     0x0D8 0x340 0x000 0x0 0x0 0x94
  1990.  
  1991.     0x0DC 0x344 0x000 0x0 0x0 0x94
  1992.  
  1993.     0x0E0 0x348 0x000 0x0 0x0 0x94
  1994.  
  1995.     0x0E4 0x34C 0x000 0x0 0x0 0x94
  1996.  
  1997.     0x0E8 0x350 0x000 0x0 0x0 0x94
  1998.    >;
  1999.   };
  2000.  
  2001.   pinctrl_usdhc2_200mhz: usdhc2grp-200mhz {
  2002.    fsl,pins = <
  2003.  
  2004.     0x0D4 0x33C 0x000 0x0 0x0 0x96
  2005.  
  2006.     0x0D8 0x340 0x000 0x0 0x0 0x96
  2007.  
  2008.     0x0DC 0x344 0x000 0x0 0x0 0x96
  2009.  
  2010.     0x0E0 0x348 0x000 0x0 0x0 0x96
  2011.  
  2012.     0x0E4 0x34C 0x000 0x0 0x0 0x96
  2013.  
  2014.     0x0E8 0x350 0x000 0x0 0x0 0x96
  2015.    >;
  2016.   };
  2017.  
  2018.   pinctrl_usdhc3_gpio: usdhc3grp-gpio {
  2019.    fsl,pins = <
  2020.  
  2021.     0x060 0x2C8 0x000 0x0 0x0 0x41
  2022.    >;
  2023.   };
  2024.  
  2025.   pinctrl_usdhc3: usdhc3grp {
  2026.    fsl,pins = <
  2027.  
  2028.     0x138 0x3A0 0x000 0x12 0x0 0x190
  2029.  
  2030.     0x13C 0x3A4 0x000 0x2 0x0 0x190
  2031.  
  2032.     0x11C 0x384 0x000 0x2 0x0 0x190
  2033.  
  2034.     0x120 0x388 0x000 0x2 0x0 0x190
  2035.  
  2036.     0x124 0x38C 0x000 0x2 0x0 0x190
  2037.  
  2038.     0x128 0x390 0x000 0x2 0x0 0x190
  2039.    >;
  2040.   };
  2041.  
  2042.   pinctrl_flexspi: flexspi0grp {
  2043.    fsl,pins = <
  2044.  
  2045.     0x0F4 0x35C 0x000 0x1 0x0 0x1c6
  2046.  
  2047.     0x0F8 0x360 0x000 0x1 0x0 0x86
  2048.  
  2049.     0x10C 0x374 0x000 0x1 0x0 0x86
  2050.  
  2051.     0x110 0x378 0x000 0x1 0x0 0x86
  2052.  
  2053.     0x114 0x37C 0x000 0x1 0x0 0x86
  2054.  
  2055.     0x118 0x380 0x000 0x1 0x0 0x86
  2056.    >;
  2057.   };
  2058.  
  2059.   pinctrl_ecspi1: ecspi1grp {
  2060.    fsl,pins = <
  2061.  
  2062.     0x1F4 0x45C 0x000 0x0 0x0 0x82
  2063.  
  2064.     0x1F8 0x460 0x000 0x0 0x0 0x82
  2065.  
  2066.     0x1FC 0x464 0x000 0x0 0x0 0x82
  2067.    >;
  2068.   };
  2069.  
  2070.   pinctrl_ecspi1_cs: ecspi1grp-cs {
  2071.    fsl,pins = <
  2072.  
  2073.     0x200 0x468 0x000 0x5 0x0 0x19
  2074.  
  2075.     0x1C0 0x428 0x000 0x5 0x0 0x19
  2076.    >;
  2077.   };
  2078.  
  2079.   pinctrl_ecspi2: ecspi2grp {
  2080.    fsl,pins = <
  2081.  
  2082.     0x204 0x46C 0x000 0x0 0x0 0x82
  2083.  
  2084.     0x208 0x470 0x000 0x0 0x0 0x82
  2085.  
  2086.     0x20C 0x474 0x000 0x0 0x0 0x82
  2087.    >;
  2088.   };
  2089.  
  2090.   pinctrl_ecspi2_cs: ecspi2grp-cs {
  2091.    fsl,pins = <
  2092.  
  2093.     0x210 0x478 0x000 0x5 0x0 0x19
  2094.  
  2095.     0x1C4 0x42C 0x000 0x5 0x0 0x19
  2096.    >;
  2097.   };
  2098.  
  2099.   pinctrl_sai1: sai1grp {
  2100.    fsl,pins = <
  2101.  
  2102.     0x184 0x3EC 0x4CC 0x0 0x3 0xd6
  2103.  
  2104.     0x164 0x3CC 0x000 0x0 0x0 0xd6
  2105.  
  2106.     0x188 0x3F0 0x4C8 0x0 0x1 0xd6
  2107.  
  2108.     0x18C 0x3F4 0x000 0x0 0x0 0xd6
  2109.    >;
  2110.   };
  2111.  
  2112.   pinctrl_sai5: sai5grp {
  2113.    fsl,pins = <
  2114.  
  2115.     0x14C 0x3B4 0x4EC 0x3 0x0 0xd6
  2116.  
  2117.     0x148 0x3B0 0x4D4 0x0 0x0 0xd6
  2118.  
  2119.     0x150 0x3B8 0x4E8 0x3 0x0 0xd6
  2120.  
  2121.     0x154 0x3BC 0x000 0x3 0x0 0xd6
  2122.    >;
  2123.   };
  2124.  
  2125.   pinctrl_pwm1: pwm1grp {
  2126.    fsl,pins = <
  2127.  
  2128.     0x1F0 0x458 0x000 0x1 0x0 0x19
  2129.    >;
  2130.   };
  2131.  
  2132.   pinctrl_pwm2: pwm2grp {
  2133.    fsl,pins = <
  2134.  
  2135.     0x1EC 0x454 0x000 0x1 0x0 0x19
  2136.    >;
  2137.   };
  2138.  
  2139.   pinctrl_pwm4: pwm4grp {
  2140.    fsl,pins = <
  2141.  
  2142.     0x1E4 0x44C 0x000 0x1 0x0 0x19
  2143.    >;
  2144.   };
  2145.  
  2146.   pinctrl_rtc1: rtc1grp {
  2147.    fsl,pins = <
  2148.  
  2149.     0x160 0x3C8 0x000 0x5 0x0 0x40000019
  2150.    >;
  2151.   };
  2152.  
  2153.   pinctrl_wifi1: wifi1grp {
  2154.    fsl,pins = <
  2155.  
  2156.     0x1B0 0x418 0x000 0x5 0x0 0x19
  2157.  
  2158.     0x170 0x3D8 0x000 0x5 0x0 0x40000019
  2159.    >;
  2160.   };
  2161.  
  2162.   pinctrl_wdog1: wdog1grp {
  2163.    fsl,pins = <
  2164.  
  2165.     0x030 0x298 0x000 0x1 0x0 0xc6
  2166.    >;
  2167.   };
  2168.  
  2169.   pinctrl_can0: can0grp {
  2170.    fsl,pins = <
  2171.  
  2172.     0x17C 0x3E4 0x000 0x5 0x0 0x19
  2173.  
  2174.     0x174 0x3DC 0x000 0x5 0x0 0x40000019
  2175.    >;
  2176.   };
  2177.  
  2178.   pinctrl_can1: can1grp {
  2179.    fsl,pins = <
  2180.  
  2181.     0x168 0x3D0 0x000 0x5 0x0 0x40000019
  2182.    >;
  2183.   };
  2184.  
  2185.   pinctrl_pcie: pciegrp {
  2186.    fsl,pins = <
  2187.  
  2188.     0x108 0x370 0x000 0x5 0x0 0x19
  2189.  
  2190.     0x130 0x398 0x000 0x5 0x0 0x40000019
  2191.    >;
  2192.   };
  2193.  
  2194.   pinctrl_lcd0_backlight: lcd0grp-backlight {
  2195.    fsl,pins = <
  2196.  
  2197.     0x190 0x3F8 0x000 0x5 0x0 0x19
  2198.    >;
  2199.   };
  2200.  
  2201.   pinctrl_lcd0_panel: lcd0grp-panel {
  2202.    fsl,pins = <
  2203.  
  2204.     0x198 0x400 0x000 0x5 0x0 0x19
  2205.    >;
  2206.   };
  2207.  
  2208.   pinctrl_lcd1_backlight: lcd1grp-backlight {
  2209.    fsl,pins = <
  2210.  
  2211.     0x194 0x3FC 0x000 0x5 0x0 0x19
  2212.    >;
  2213.   };
  2214.  
  2215.   pinctrl_lcd1_panel: lcd1grp-panel {
  2216.    fsl,pins = <
  2217.  
  2218.     0x19C 0x404 0x000 0x5 0x0 0x19
  2219.    >;
  2220.   };
  2221.  
  2222.   pinctrl_lvds_bridge: lvdsgrp-bridge {
  2223.    fsl,pins = <
  2224.  
  2225.     0x15C 0x3C4 0x000 0x5 0x0 0x19
  2226.  
  2227.     0x16C 0x3D4 0x000 0x5 0x0 0x40000019
  2228.    >;
  2229.   };
  2230.  
  2231.   pinctrl_usbotg1: usbotg1grp {
  2232.    fsl,pins = <
  2233.  
  2234.     0x058 0x2C0 0x000 0x1 0x0 0x19
  2235.  
  2236.     0x05C 0x2C4 0x000 0x1 0x0 0x40000019
  2237.    >;
  2238.   };
  2239.  
  2240.   pinctrl_usbotg2: usbotg2grp {
  2241.    fsl,pins = <
  2242.  
  2243.     0x134 0x39C 0x000 0x5 0x0 0x40000019
  2244.  
  2245.     0x104 0x36C 0x000 0x5 0x0 0x19
  2246.    >;
  2247.   };
  2248.  
  2249.   pinctrl_tpm: tpmgrp {
  2250.    fsl,pins = <
  2251.  
  2252.     0x060 0x2C8 0x000 0x0 0x0 0x40000019
  2253.    >;
  2254.   };
  2255.  
  2256.   pinctrl_cam: camgrp {
  2257.    fsl,pins = <
  2258.  
  2259.     0x028 0x290 0x000 0x0 0x0 0x40000019
  2260.  
  2261.     0x034 0x29C 0x000 0x0 0x0 0x40000019
  2262.    >;
  2263.   };
  2264.  };
  2265. };
  2266.  
  2267. / {
  2268.  model = "MSC SM2S-IMX8MM";
  2269.  compatible = "msc,sm2s-imx8mm", "fsl,imx8mm";
  2270.  
  2271.  chosen {
  2272.   bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200";
  2273.   stdout-path = &uart1;
  2274.  };
  2275.  
  2276.  busfreq {
  2277.   status = "disabled";
  2278.  };
  2279.  
  2280.  aliases {
  2281.   i2c4 = &i2c_cam;
  2282.  };
  2283.  
  2284.  regulators {
  2285.   compatible = "simple-bus";
  2286.   #address-cells = <1>;
  2287.   #size-cells = <0>;
  2288.  
  2289.   reg_otg1_vbus: otg1_vbus_regulator {
  2290.    compatible = "regulator-fixed";
  2291.    regulator-name = "OTG1_VBUS";
  2292.    regulator-min-microvolt = <1800000>;
  2293.    regulator-max-microvolt = <1800000>;
  2294.    gpio = <&gpio1 12 0>;
  2295.    enable-active-high;
  2296.   };
  2297.  
  2298.   reg_usdhc2_vmmc: regulator-usdhc2 {
  2299.    compatible = "regulator-fixed";
  2300.    regulator-name = "VSD_3V3";
  2301.    regulator-min-microvolt = <3300000>;
  2302.    regulator-max-microvolt = <3300000>;
  2303.    gpio = <&gpio2 19 0>;
  2304.    enable-active-high;
  2305.    startup-delay-us = <100>;
  2306.    u-boot,off-on-delay-us = <12000>;
  2307.   };
  2308.  };
  2309.  
  2310.  clocks {
  2311.  
  2312.   clk_out_1: clock@10 {
  2313.    compatible = "fixed-clock";
  2314.    reg = <10>;
  2315.    #clock-cells = <0>;
  2316.    clock-frequency = <24000000>;
  2317.    clock-output-names = "clk_out_1";
  2318.   };
  2319.  
  2320.  
  2321.   clk_out_2: clock@11 {
  2322.    compatible = "fixed-clock";
  2323.    reg = <11>;
  2324.    #clock-cells = <0>;
  2325.    clock-frequency = <24000000>;
  2326.    clock-output-names = "clk_out_2";
  2327.   };
  2328.  
  2329.   osc_can0: clock@12 {
  2330.    compatible = "fixed-clock";
  2331.    reg = <12>;
  2332.    #clock-cells = <0>;
  2333.    clock-frequency = <20000000>;
  2334.    clock-output-names = "osc_can0";
  2335.   };
  2336.  
  2337.   osc_can1: clock@13 {
  2338.    compatible = "fixed-clock";
  2339.    reg = <13>;
  2340.    #clock-cells = <0>;
  2341.    clock-frequency = <20000000>;
  2342.    clock-output-names = "osc_can1";
  2343.   };
  2344.  };
  2345.  
  2346.  i2c_cam: i2c_cam {
  2347.   pinctrl-names = "default";
  2348.   pinctrl-0 = <&pinctrl_i2c_cam>;
  2349.   compatible = "i2c-gpio";
  2350.   #address-cells = <1>;
  2351.   #size-cells = <0>;
  2352.   sda-gpios = <&gpio5 25 (0 | (2 | 4))>;
  2353.   scl-gpios = <&gpio5 24 (0 | (2 | 4))>;
  2354.   i2c-gpio,delay-us = <2>;
  2355.   status = "okay";
  2356.  };
  2357.  
  2358.  lcd0_backlight: lcd0_backlight {
  2359.   pinctrl-names = "default";
  2360.   pinctrl-0 = <&pinctrl_lcd0_backlight>;
  2361.   compatible = "pwm-backlight";
  2362.   pwms = <&pwm1 0 1000000 0>;
  2363.   brightness-levels = <
  2364.      0 1 2 3 4 5 6 7 8 9
  2365.     10 11 12 13 14 15 16 17 18 19
  2366.     20 21 22 23 24 25 26 27 28 29
  2367.     30 31 32 33 34 35 36 37 38 39
  2368.     40 41 42 43 44 45 46 47 48 49
  2369.     50 51 52 53 54 55 56 57 58 59
  2370.     60 61 62 63 64 65 66 67 68 69
  2371.     70 71 72 73 74 75 76 77 78 79
  2372.     80 81 82 83 84 85 86 87 88 89
  2373.     90 91 92 93 94 95 96 97 98 99
  2374.    100 101 102 103 104 105 106 107 108 109
  2375.    110 111 112 113 114 115 116 117 118 119
  2376.    120 121 122 123 124 125 126 127 128 129
  2377.    130 131 132 133 134 135 136 137 138 139
  2378.    140 141 142 143 144 145 146 147 148 149
  2379.    150 151 152 153 154 155 156 157 158 159
  2380.    160 161 162 163 164 165 166 167 168 169
  2381.    170 171 172 173 174 175 176 177 178 179
  2382.    180 181 182 183 184 185 186 187 188 189
  2383.    190 191 192 193 194 195 196 197 198 199
  2384.    200 201 202 203 204 205 206 207 208 209
  2385.    210 211 212 213 214 215 216 217 218 219
  2386.    220 221 222 223 224 225 226 227 228 229
  2387.    230 231 232 233 234 235 236 237 238 239
  2388.    240 241 242 243 244 245 246 247 248 249
  2389.    250 251 252 253 254 255
  2390.   >;
  2391.   default-brightness-level = <255>;
  2392.   enable-gpios = <&gpio4 13 0>;
  2393.   status = "disabled";
  2394.  };
  2395.  
  2396.  lcd1_backlight: lcd1_backlight {
  2397.   pinctrl-names = "default";
  2398.   pinctrl-0 = <&pinctrl_lcd1_backlight>;
  2399.   compatible = "pwm-backlight";
  2400.   pwms = <&pwm2 0 1000000>;
  2401.   brightness-levels = <
  2402.      0 1 2 3 4 5 6 7 8 9
  2403.     10 11 12 13 14 15 16 17 18 19
  2404.     20 21 22 23 24 25 26 27 28 29
  2405.     30 31 32 33 34 35 36 37 38 39
  2406.     40 41 42 43 44 45 46 47 48 49
  2407.     50 51 52 53 54 55 56 57 58 59
  2408.     60 61 62 63 64 65 66 67 68 69
  2409.     70 71 72 73 74 75 76 77 78 79
  2410.     80 81 82 83 84 85 86 87 88 89
  2411.     90 91 92 93 94 95 96 97 98 99
  2412.    100 101 102 103 104 105 106 107 108 109
  2413.    110 111 112 113 114 115 116 117 118 119
  2414.    120 121 122 123 124 125 126 127 128 129
  2415.    130 131 132 133 134 135 136 137 138 139
  2416.    140 141 142 143 144 145 146 147 148 149
  2417.    150 151 152 153 154 155 156 157 158 159
  2418.    160 161 162 163 164 165 166 167 168 169
  2419.    170 171 172 173 174 175 176 177 178 179
  2420.    180 181 182 183 184 185 186 187 188 189
  2421.    190 191 192 193 194 195 196 197 198 199
  2422.    200 201 202 203 204 205 206 207 208 209
  2423.    210 211 212 213 214 215 216 217 218 219
  2424.    220 221 222 223 224 225 226 227 228 229
  2425.    230 231 232 233 234 235 236 237 238 239
  2426.    240 241 242 243 244 245 246 247 248 249
  2427.    250 251 252 253 254 255
  2428.   >;
  2429.   default-brightness-level = <255>;
  2430.   enable-gpios = <&gpio4 19 0>;
  2431.   status = "disabled";
  2432.  };
  2433.  
  2434.  user_gpios {
  2435.                 compatible = "msc,user-gpios";
  2436.  
  2437.  
  2438.  
  2439.  
  2440.  
  2441.                 GPIO0-gpios = <&gpio1 0 0>;
  2442.                 GPIO1-gpios = <&gpio1 1 0>;
  2443.                 GPIO2-gpios = <&gpio1 3 0>;
  2444.                 GPIO3-gpios = <&gpio1 5 0>;
  2445.                 GPIO4-gpios = <&gpio1 6 0>;
  2446.                 GPIO5-gpios = <&gpio5 2 0>;
  2447.                 GPIO6-gpios = <&gpio5 1 0>;
  2448.                 GPIO7-gpios = <&gpio4 22 0>;
  2449.                 GPIO8-gpios = <&gpio3 25 0>;
  2450.                 GPIO9-gpios = <&gpio4 28 0>;
  2451.                 GPIO10-gpios = <&gpio1 9 0>;
  2452.                 GPIO11-gpios = <&gpio1 7 0>;
  2453.         };
  2454. };
  2455.  
  2456. &fec1 {
  2457.  pinctrl-names = "default";
  2458.  pinctrl-0 = <&pinctrl_fec1>;
  2459.  phy-mode = "rgmii-id";
  2460.  phy-handle = <&ethphy1>;
  2461.  fsl,magic-packet;
  2462.  status = "okay";
  2463.  
  2464.  mdio {
  2465.   #address-cells = <1>;
  2466.   #size-cells = <0>;
  2467.  
  2468.   ethphy1: ethernet-phy@1 {
  2469.    reg = <1>;
  2470.    compatible = "ethernet-phy-id2000.a231";
  2471.    ti,rx-internal-delay = <0x8>;
  2472.    ti,tx-internal-delay = <0xa>;
  2473.    ti,fifo-depth = <0x01>;
  2474.  
  2475.  
  2476.  
  2477.    ti,led-gpio-polarity-active-high;
  2478.    ti,led-2-polarity-active-high;
  2479.    ti,led-1-polarity-active-high;
  2480.    ti,led-0-polarity-active-high;
  2481.   };
  2482.  };
  2483. };
  2484.  
  2485.  
  2486. &i2c1 {
  2487.  clock-frequency = <400000>;
  2488.  pinctrl-names = "default";
  2489.  pinctrl-0 = <&pinctrl_i2c1>;
  2490.  status = "okay";
  2491.  
  2492.  pmic1: pmic@31 {
  2493.   compatible = "ricoh,rn5t567";
  2494.   reg = <0x31>;
  2495.   pmic-id = <0>;
  2496.   system-restart-controller;
  2497.   sleep-sequence = /bits/ 8 <
  2498.     0x16 0x2b
  2499.     0x17 0x49
  2500.     0x1b 0x2b
  2501.     0x1c 0x67
  2502.     0x1f 0x0b
  2503.     0x32 0x03
  2504.     0x30 0x03
  2505.    >;
  2506.  
  2507.   regulators {
  2508.    DCDC1 {
  2509.     regulator-name = "VCC_DRAM_VPU_0V9";
  2510.     regulator-always-on;
  2511.     regulator-min-microvolt = <900000>;
  2512.     regulator-max-microvolt = <900000>;
  2513.    };
  2514.    DCDC2 {
  2515.     regulator-name = "VCC_ARM_0V9";
  2516.     regulator-always-on;
  2517.     regulator-min-microvolt = <900000>;
  2518.     regulator-max-microvolt = <900000>;
  2519.    };
  2520.    DCDC3 {
  2521.     regulator-name = "VCCA_1V8";
  2522.     regulator-always-on;
  2523.     regulator-min-microvolt = <1800000>;
  2524.     regulator-max-microvolt = <1800000>;
  2525.    };
  2526.    DCDC4 {
  2527.     regulator-name = "VCC_SOC_0V85";
  2528.     regulator-always-on;
  2529.     regulator-min-microvolt = <850000>;
  2530.     regulator-max-microvolt = <850000>;
  2531.    };
  2532.    LDO1 {
  2533.     regulator-name = "VCC_PHY_0V9";
  2534.     regulator-always-on;
  2535.     regulator-min-microvolt = <900000>;
  2536.     regulator-max-microvolt = <900000>;
  2537.    };
  2538.    LDO2 {
  2539.     regulator-name = "VCC_LDO12_1V2";
  2540.     regulator-always-on;
  2541.     regulator-min-microvolt = <1200000>;
  2542.     regulator-max-microvolt = <1200000>;
  2543.    };
  2544.    LDO3 {
  2545.     regulator-name = "VCC_LDO13_3V3";
  2546.     regulator-always-on;
  2547.     regulator-min-microvolt = <3300000>;
  2548.     regulator-max-microvolt = <3300000>;
  2549.    };
  2550.    LDO4 {
  2551.     regulator-name = "VCC_LDO14_3V3";
  2552.     regulator-always-on;
  2553.     regulator-min-microvolt = <3300000>;
  2554.     regulator-max-microvolt = <3300000>;
  2555.    };
  2556.    LDO5 {
  2557.     regulator-name = "VCC_LDO15_1V8";
  2558.     regulator-always-on;
  2559.     regulator-min-microvolt = <1800000>;
  2560.     regulator-max-microvolt = <1800000>;
  2561.    };
  2562.    LDORTC1 {
  2563.     regulator-name = "VCC_SNVS_1V8";
  2564.     regulator-always-on;
  2565.     regulator-min-microvolt = <1800000>;
  2566.     regulator-max-microvolt = <1800000>;
  2567.    };
  2568.    LDORTC2 {
  2569.     regulator-name = "VCC_PM1_SNVS_3V3";
  2570.     regulator-always-on;
  2571.     regulator-min-microvolt = <3300000>;
  2572.     regulator-max-microvolt = <3300000>;
  2573.    };
  2574.   };
  2575.  };
  2576.  
  2577.  rtc: rtc@32 {
  2578.   compatible = "ricoh,r2221tl";
  2579.   pinctrl-names = "default";
  2580.   pinctrl-0 = <&pinctrl_rtc1>;
  2581.   reg = <0x32>;
  2582.  };
  2583.  
  2584.  pmic2: pmic@33 {
  2585.   compatible = "ricoh,rn5t567";
  2586.   reg = <0x33>;
  2587.   pmic-id = <1>;
  2588.   sleep-sequence = /bits/ 8 <
  2589.     0x16 0x45
  2590.     0x19 0x63
  2591.     0x1c 0x63
  2592.     0x1d 0x45
  2593.     0x1e 0xa1
  2594.     0x1f 0xa1
  2595.     0x30 0x03
  2596.     0x2e 0x03
  2597.    >;
  2598.  
  2599.   regulators {
  2600.    DCDC1 {
  2601.     regulator-name = "VCC_3V3";
  2602.     regulator-always-on;
  2603.     regulator-min-microvolt = <3300000>;
  2604.     regulator-max-microvolt = <3300000>;
  2605.    };
  2606.    DCDC2 {
  2607.     regulator-name = "VCC_1V8";
  2608.     regulator-always-on;
  2609.     regulator-min-microvolt = <1800000>;
  2610.     regulator-max-microvolt = <1800000>;
  2611.    };
  2612.    DCDC3 {
  2613.     regulator-name = "VCC_DRAM_1V1";
  2614.     regulator-always-on;
  2615.     regulator-min-microvolt = <1100000>;
  2616.     regulator-max-microvolt = <1100000>;
  2617.    };
  2618.    DCDC4 {
  2619.     regulator-name = "VCC_ETH_1V0";
  2620.     regulator-always-on;
  2621.     regulator-min-microvolt = <1000000>;
  2622.     regulator-max-microvolt = <1000000>;
  2623.    };
  2624.    LDO1 {
  2625.     regulator-name = "VCC_PHY_1V2";
  2626.     regulator-always-on;
  2627.     regulator-min-microvolt = <1200000>;
  2628.     regulator-max-microvolt = <1200000>;
  2629.    };
  2630.    LDO2 {
  2631.     regulator-name = "VCC_ETH_2V5";
  2632.     regulator-always-on;
  2633.     regulator-min-microvolt = <2500000>;
  2634.     regulator-max-microvolt = <2500000>;
  2635.    };
  2636.    LDO3 {
  2637.     regulator-name = "VCC_USB_1V1";
  2638.     regulator-always-on;
  2639.     regulator-min-microvolt = <1100000>;
  2640.     regulator-max-microvolt = <1100000>;
  2641.    };
  2642.    LDO4 {
  2643.     regulator-name = "VCC_LDO24_1V8";
  2644.     regulator-always-on;
  2645.     regulator-min-microvolt = <1800000>;
  2646.     regulator-max-microvolt = <1800000>;
  2647.    };
  2648.    LDO5 {
  2649.     regulator-name = "VCC_LDO25_1V8";
  2650.     regulator-always-on;
  2651.     regulator-min-microvolt = <1800000>;
  2652.     regulator-max-microvolt = <1800000>;
  2653.    };
  2654.    LDORTC1 {
  2655.     regulator-name = "VCC_PM2_SNVS_3V3";
  2656.     regulator-always-on;
  2657.     regulator-min-microvolt = <3300000>;
  2658.     regulator-max-microvolt = <3300000>;
  2659.    };
  2660.    LDORTC2 {
  2661.     regulator-name = "VCC_SNVS_0V9";
  2662.     regulator-always-on;
  2663.     regulator-min-microvolt = <900000>;
  2664.     regulator-max-microvolt = <900000>;
  2665.    };
  2666.   };
  2667.  };
  2668.  
  2669.  tmp103: tmp103@71 {
  2670.   compatible = "ti,tmp103";
  2671.   reg = <0x71>;
  2672.  };
  2673.  
  2674.  dsi_lvds_bridge: sn65dsi84@2d {
  2675.   compatible = "ti,sn65dsi83";
  2676.   reg = <0x2d>;
  2677.   pinctrl-names = "default";
  2678.   pinctrl-0 = <&pinctrl_lvds_bridge>, <&pinctrl_lcd0_panel>;
  2679.   enable-gpios = <&gpio4 0 0>;
  2680.   enable-panel-gpios = <&gpio4 15 0>;
  2681.   interrupts-extended = <&gpio4 4 4>;
  2682.   status = "disabled";
  2683.  };
  2684.  
  2685. };
  2686.  
  2687.  
  2688. &i2c2 {
  2689.  clock-frequency = <400000>;
  2690.  pinctrl-names = "default";
  2691.  pinctrl-0 = <&pinctrl_i2c2>;
  2692.  status = "okay";
  2693. };
  2694.  
  2695.  
  2696. &i2c3 {
  2697.  clock-frequency = <100000>;
  2698.  pinctrl-names = "default";
  2699.  pinctrl-0 = <&pinctrl_i2c3>;
  2700.  status = "okay";
  2701.  
  2702.  module_eeprom@0x50 {
  2703.   compatible = "atmel,24c64";
  2704.   reg = <0x50>;
  2705.   pagesize = <32>;
  2706.  };
  2707. };
  2708.  
  2709.  
  2710. &i2c4 {
  2711.  clock-frequency = <100000>;
  2712.  pinctrl-names = "default";
  2713.  pinctrl-0 = <&pinctrl_i2c4>;
  2714.  status = "okay";
  2715. };
  2716.  
  2717.  
  2718. &uart1 {
  2719.  pinctrl-names = "default";
  2720.  pinctrl-0 = <&pinctrl_uart1>;
  2721.  fsl,uart-has-rtscts;
  2722.  rts-gpios = <&gpio4 24 1>;
  2723.  cts-gpios = <&gpio4 23 1>;
  2724.  status = "okay";
  2725. };
  2726.  
  2727.  
  2728. &uart2 {
  2729.  pinctrl-names = "default";
  2730.  pinctrl-0 = <&pinctrl_uart2>;
  2731.  fsl,uart-has-rtscts;
  2732.  rts-gpios = <&gpio4 30 1>;
  2733.  cts-gpios = <&gpio4 29 1>;
  2734.  status = "okay";
  2735. };
  2736.  
  2737.  
  2738. &uart3 {
  2739.  pinctrl-names = "default";
  2740.  pinctrl-0 = <&pinctrl_uart3>;
  2741.  status = "okay";
  2742. };
  2743.  
  2744.  
  2745. &uart4 {
  2746.  pinctrl-names = "default";
  2747.  pinctrl-0 = <&pinctrl_uart4>;
  2748.  status = "okay";
  2749. };
  2750.  
  2751. &flexspi {
  2752.  pinctrl-names = "default";
  2753.  pinctrl-0 = <&pinctrl_flexspi>;
  2754.  status = "disabled";
  2755.  
  2756.  flash0: w25q32@0 {
  2757.   reg = <0>;
  2758.   #address-cells = <1>;
  2759.   #size-cells = <1>;
  2760.   compatible = "jedec,spi-nor";
  2761.   spi-max-frequency = <29000000>;
  2762.   spi-nor,ddr-quad-read-dummy = <6>;
  2763.  };
  2764. };
  2765.  
  2766. &ecspi1 {
  2767.  #address-cells = <1>;
  2768.  #size-cells = <0>;
  2769.  fsl,spi-num-chipselects = <2>;
  2770.  pinctrl-names = "default";
  2771.  pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_ecspi1_cs>;
  2772.  cs-gpios =
  2773.    <&gpio5 9 1>,
  2774.    <&gpio4 25 1>;
  2775.  status = "okay";
  2776.  
  2777.  can0: can@1 {
  2778.   compatible = "microchip,mcp2515";
  2779.   reg = <1>;
  2780.   pinctrl-names = "default";
  2781.   pinctrl-0 = <&pinctrl_can0>;
  2782.   clocks = <&osc_can0>;
  2783.   interrupt-parent = <&gpio4>;
  2784.   interrupts = <6 2>;
  2785.   reset-gpio = <&gpio4 8 1>;
  2786.   spi-max-frequency= <10000000>;
  2787.   status = "disabled";
  2788.  };
  2789. };
  2790.  
  2791. &ecspi2 {
  2792.  #address-cells = <1>;
  2793.  #size-cells = <0>;
  2794.  fsl,spi-num-chipselects = <2>;
  2795.  pinctrl-names = "default";
  2796.  pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_ecspi2_cs>;
  2797.  cs-gpios =
  2798.    <&gpio5 13 1>,
  2799.    <&gpio4 26 1>;
  2800.  status = "okay";
  2801.  
  2802.  can1: can@1 {
  2803.   compatible = "microchip,mcp2515";
  2804.   reg = <1>;
  2805.   pinctrl-names = "default";
  2806.   pinctrl-0 = <&pinctrl_can1>;
  2807.   clocks = <&osc_can1>;
  2808.   interrupt-parent = <&gpio4>;
  2809.   interrupts = <3 2>;
  2810.   spi-max-frequency= <10000000>;
  2811.   status = "disabled";
  2812.  };
  2813. };
  2814.  
  2815. &usdhc1 {
  2816.  pinctrl-names = "default", "state_100mhz", "state_200mhz";
  2817.  pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_reset>;
  2818.  pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_reset>;
  2819.  pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_reset>;
  2820.  bus-width = <8>;
  2821.  non-removable;
  2822.  status = "okay";
  2823. };
  2824.  
  2825. &usdhc2 {
  2826.  pinctrl-names = "default", "state_100mhz", "state_200mhz";
  2827.  pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  2828.  pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  2829.  pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  2830.  bus-width = <4>;
  2831.  cd-gpios = <&gpio2 12 1>;
  2832.  wp-gpios = <&gpio2 20 0>;
  2833.  vmmc-supply = <&reg_usdhc2_vmmc>;
  2834.  no-1-8-v;
  2835.  status = "okay";
  2836. };
  2837.  
  2838. &usdhc3 {
  2839.  pinctrl-names = "default";
  2840.  pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
  2841.  bus-width = <4>;
  2842.  cd-gpios = <&gpio1 14 1>;
  2843.  status = "disabled";
  2844. };
  2845.  
  2846. &usbotg1 {
  2847.  pinctrl-names = "default";
  2848.  pinctrl-0 = <&pinctrl_usbotg1>;
  2849.  power-polarity-active-high;
  2850.  dr_mode = "otg";
  2851.  status = "okay";
  2852. };
  2853.  
  2854. &usbotg2 {
  2855.  pinctrl-names = "default";
  2856.  pinctrl-0 = <&pinctrl_usbotg2>;
  2857.  dr_mode = "host";
  2858.  status = "okay";
  2859. };
  2860.  
  2861. &pwm1 {
  2862.  pinctrl-names = "default";
  2863.  pinctrl-0 = <&pinctrl_pwm1>;
  2864.  status = "disabled";
  2865. };
  2866.  
  2867. &pwm2 {
  2868.  pinctrl-names = "default";
  2869.  pinctrl-0 = <&pinctrl_pwm2>;
  2870.  status = "disabled";
  2871. };
  2872.  
  2873. &pwm4 {
  2874.  pinctrl-names = "default";
  2875.  pinctrl-0 = <&pinctrl_pwm4>;
  2876.  status = "disabled";
  2877. };
  2878.  
  2879. &wdog1 {
  2880.  pinctrl-names = "default";
  2881.  pinctrl-0 = <&pinctrl_wdog1>;
  2882.  fsl,ext-reset-output;
  2883.  status = "okay";
  2884. };
  2885.  
  2886. &pcie0 {
  2887.  pinctrl-names = "default";
  2888.  pinctrl-0 = <&pinctrl_pcie>;
  2889.  reset-gpio = <&gpio3 5 1>;
  2890.  ext_osc = <0>;
  2891.  status = "okay";
  2892. };
  2893.  
  2894. &sai5 {
  2895.  pinctrl-names = "default";
  2896.  pinctrl-0 = <&pinctrl_sai5>;
  2897.  status = "disabled";
  2898. };
  2899.  
  2900. &mipi_csi_1 {
  2901.  #address-cells = <1>;
  2902.  #size-cells = <0>;
  2903.  status = "disabled";
  2904.  port {
  2905.   mipi1_sensor_ep: endpoint@1 {
  2906.   };
  2907.  
  2908.   csi1_mipi_ep: endpoint@2 {
  2909.    remote-endpoint = <&csi1_ep>;
  2910.   };
  2911.  };
  2912. };
  2913.  
  2914. &csi1_bridge {
  2915.  fsl,mipi-mode;
  2916.  status = "disabled";
  2917.  port {
  2918.   csi1_ep: endpoint {
  2919.    remote-endpoint = <&csi1_mipi_ep>;
  2920.   };
  2921.  };
  2922. };
  2923.  
  2924. &snvs_pwrkey {
  2925.  on-time = <3>;
  2926. };
  2927.  
  2928. &anatop {
  2929.  video-pll1-ss,enable;
  2930.  video-pll1-ss,ffin_MHz = <24>;
  2931.  video-pll1-ss,mf_kHz = <30>;
  2932.  
  2933. };
  2934.  
  2935. &cpu_alert0 {
  2936.  temperature = <95000>;
  2937. };
  2938.  
  2939. &cpu_crit0 {
  2940.  temperature = <105000>;
  2941. };
  2942. # 15 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-14N0261I-base.dtsi" 2
  2943. # 1 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-wifi.dtsi" 1
  2944. # 14 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-wifi.dtsi"
  2945. &usdhc3 {
  2946.  pinctrl-names = "default";
  2947.  pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>, <&pinctrl_wifi1>;
  2948.  bus-width = <4>;
  2949.  wifi-host;
  2950.  keep-power-in-suspend;
  2951.  no-1-8-v;
  2952.  non-removable;
  2953.  pm-ignore-notify;
  2954.  post-power-on-delay-ms = <100>;
  2955.  status = "okay";
  2956. };
  2957.  
  2958. &gpio4 {
  2959.  wifi_pdn {
  2960.   gpio-hog;
  2961.   gpios = <21 1>;
  2962.   output-low;
  2963.   line-name = "wifi_pdn";
  2964.  };
  2965. };
  2966. # 16 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-14N0261I-base.dtsi" 2
  2967.  
  2968. / {
  2969.  memory@40000000 {
  2970.  
  2971.   reg = <0x0 0x40000000 0 0x80000000>;
  2972.  };
  2973. };
  2974.  
  2975. &can0 {
  2976.  status = "okay";
  2977. };
  2978.  
  2979. &can1 {
  2980.  status = "okay";
  2981. };
  2982. # 15 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-14N0261I-headless.dts" 2
  2983. # 1 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-ep1.dtsi" 1
  2984. # 14 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-ep1.dtsi"
  2985. &iomuxc {
  2986.  
  2987.  pinctrl-names = "default";
  2988.  pinctrl-0 = <&pinctrl_hog>, <&pinctrl_ep1_gpio>;
  2989.  
  2990.  sm2s-imx8mm {
  2991.  
  2992.   pinctrl_ep1_gpio: ep1grp-gpio {
  2993.  
  2994.    fsl,pins = <
  2995.  
  2996.     0x02C 0x294 0x000 0x0 0x0 0x40000019
  2997.  
  2998.     0x03C 0x2A4 0x000 0x0 0x0 0x19
  2999.  
  3000.     0x1B4 0x41C 0x000 0x5 0x0 0x40000019
  3001.  
  3002.     0x158 0x3C0 0x000 0x5 0x0 0x40000019
  3003.  
  3004.     0x1CC 0x434 0x000 0x5 0x0 0x40000019
  3005.  
  3006.     0x04C 0x2B4 0x000 0x0 0x0 0x40000019
  3007.  
  3008.     0x044 0x2AC 0x000 0x0 0x0 0x40000019
  3009.    >;
  3010.   };
  3011.  };
  3012. };
  3013.  
  3014. / {
  3015.  regulators {
  3016.   compatible = "simple-bus";
  3017.   #address-cells = <1>;
  3018.   #size-cells = <0>;
  3019.  
  3020.   reg_vcc_3v3_aud: vcc_3v3_aud_regulator {
  3021.    compatible = "regulator-fixed";
  3022.    regulator-name = "3V3_AUD";
  3023.    regulator-min-microvolt = <3300000>;
  3024.    regulator-max-microvolt = <3300000>;
  3025.   };
  3026.  
  3027.   reg_vcc_1v8_aud: vcc_1v8_aud_regulator {
  3028.    compatible = "regulator-fixed";
  3029.    regulator-name = "1V8_AUD";
  3030.    regulator-min-microvolt = <1800000>;
  3031.    regulator-max-microvolt = <1800000>;
  3032.   };
  3033.  };
  3034.  
  3035.  sgtl5000_sound: sgtl5000-sound {
  3036.   compatible = "fsl,imx-audio-sgtl5000";
  3037.   model = "imx-sgtl5000";
  3038.   audio-cpu = <&sai5>;
  3039.   audio-codec = <&sgtl5000_codec>;
  3040.   audio-routing =
  3041.     "LINE_IN", "Line In Jack",
  3042.     "MIC_IN", "Mic Jack",
  3043.     "Mic Jack", "Mic Bias",
  3044.     "Headphone Jack", "HP_OUT";
  3045.  };
  3046.  
  3047.  pwm-fan {
  3048.   compatible = "pwm-fan";
  3049.   pwms = <&pwm4 0 1000000>;
  3050.   interrupt-parent = <&gpio5>;
  3051.   interrupts = <1 2>;
  3052.   pulses-per-revolution = <2>;
  3053.  };
  3054. };
  3055.  
  3056. &pwm4 {
  3057.  status = "okay";
  3058. };
  3059.  
  3060. &anatop {
  3061.  
  3062.  clkout1,enable;
  3063.  
  3064.  clkout2,enable;
  3065. };
  3066.  
  3067. &i2c3 {
  3068.  sgtl5000_codec: sgtl5000@0a {
  3069.   compatible = "fsl,sgtl5000";
  3070.   reg = <0x0a>;
  3071.   clocks = <&clk_out_1>;
  3072.   clock-names = "audio_mclk";
  3073.   VDDA-supply = <&reg_vcc_3v3_aud>;
  3074.   VDD-supply = <&reg_vcc_1v8_aud>;
  3075.   VDDIO-supply = <&reg_vcc_1v8_aud>;
  3076.  };
  3077.  edt-ft5x06@38 {
  3078.         compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
  3079.         reg = <0x38>;
  3080.   pinctrl-names = "default";
  3081.         interrupt-parent = <&gpio1>;
  3082.         interrupts = <1 2>;
  3083.         reset-gpios = <&gpio1 9 1>;
  3084.   touchscreen-size-x = <720>;
  3085.         touchscreen-size-y = <1280>;
  3086.  
  3087.  };
  3088.  gt911@5d {
  3089.         compatible = "goodix,gt911";
  3090.         reg = <0x5d>;
  3091.         interrupt-parent = <&gpio1>;
  3092.         interrupts = <1 0>;
  3093.         irq-gpios = <&gpio1 1 0>;
  3094.         reset-gpios = <&gpio1 9 0>;
  3095.     };
  3096. };
  3097.  
  3098. &sai5 {
  3099.  status = "okay";
  3100. };
  3101.  
  3102.  
  3103. &ecspi1 {
  3104.  flash1_1: m25p80@0 {
  3105.   #address-cells = <1>;
  3106.   #size-cells = <1>;
  3107.   compatible = "jedec,spi-nor";
  3108.   reg = <0>;
  3109.   spi-max-frequency = <20000000>;
  3110.   status = "okay";
  3111.  };
  3112.  
  3113.  flash1_2: m25p80@1 {
  3114.   #address-cells = <1>;
  3115.   #size-cells = <1>;
  3116.   compatible = "jedec,spi-nor";
  3117.   reg = <1>;
  3118.   spi-max-frequency = <20000000>;
  3119.   status = "okay";
  3120.  };
  3121. };
  3122.  
  3123.  
  3124. &ecspi2 {
  3125.  flash2_1: m25p80@0 {
  3126.   #address-cells = <1>;
  3127.   #size-cells = <1>;
  3128.   compatible = "jedec,spi-nor";
  3129.   reg = <0>;
  3130.   spi-max-frequency = <20000000>;
  3131.   status = "okay";
  3132.  };
  3133.  
  3134.  flash2_2: m25p80@1 {
  3135.   #address-cells = <1>;
  3136.   #size-cells = <1>;
  3137.   compatible = "jedec,spi-nor";
  3138.   reg = <1>;
  3139.   spi-max-frequency = <20000000>;
  3140.   status = "okay";
  3141.  };
  3142. };
  3143.  
  3144. &mipi_csi_1 {
  3145.  status = "okay";
  3146.  port {
  3147.   mipi1_sensor_ep: endpoint@1 {
  3148.    remote-endpoint = <&ov5640_mipi1_ep>;
  3149.    data-lanes = <2>;
  3150.    csis-hs-settle = <13>;
  3151.    csis-clk-settle = <2>;
  3152.    csis-wclk;
  3153.   };
  3154.  };
  3155. };
  3156.  
  3157. &csi1_bridge {
  3158.  status = "okay";
  3159. };
  3160.  
  3161. &i2c_cam {
  3162.  ov5640_mipi: ov5640_mipi@3c {
  3163.   compatible = "ovti,ov5640_mipi";
  3164.   reg = <0x3c>;
  3165.   status = "okay";
  3166.   pinctrl-names = "default";
  3167.   pinctrl-0 = <&pinctrl_cam>;
  3168.   clocks = <&clk_out_2>;
  3169.   clock-names = "csi_mclk";
  3170.   csi_id = <0>;
  3171.   pwn-gpios = <&gpio1 0 1>;
  3172.   rst-gpios = <&gpio1 3 1>;
  3173.   mclk = <24000000>;
  3174.   mclk_source = <0>;
  3175.   port {
  3176.    ov5640_mipi1_ep: endpoint {
  3177.     remote-endpoint = <&mipi1_sensor_ep>;
  3178.    };
  3179.   };
  3180.  };
  3181. };
  3182. # 16 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-14N0261I-headless.dts" 2
  3183.  
  3184. # 1 "arch/arm64/boot/dts/msc/imx8mm/../common/panel-lcdif-mipi-ph720128t003.dtsi" 1
  3185. # 14 "arch/arm64/boot/dts/msc/imx8mm/../common/panel-lcdif-mipi-ph720128t003.dtsi"
  3186. &dsi {
  3187.     status = "okay";
  3188.     ports {
  3189.         port@1 {
  3190.             dsi_out_panel: endpoint {
  3191.                 remote-endpoint = <&panel_in>;
  3192.             };
  3193.         };
  3194.     };
  3195. };
  3196.  
  3197. / {
  3198.     panel@0 {
  3199.         pinctrl-names = "default";
  3200.         compatible = "powertip,ph720128t003";
  3201.         enable-gpios = <&gpio4 28 0>;
  3202.         reset-gpios = <&gpio4 15 0>;
  3203.         backlight = <&lcd0_backlight>;
  3204.         status = "okay";
  3205.         port {
  3206.                 panel_in: endpoint {
  3207.                         remote-endpoint = <&dsi_out_panel>;
  3208.                 };
  3209.         };
  3210.  
  3211.     };
  3212. };
  3213.  
  3214. &lcdif {
  3215.         status = "okay";
  3216. };
  3217.  
  3218. &gpu_2d {
  3219.         status = "okay";
  3220. };
  3221.  
  3222. &gpu_3d {
  3223.         status = "okay";
  3224. };
  3225.  
  3226. &vpu_g1 {
  3227.         status = "okay";
  3228. };
  3229.  
  3230. &vpu_g2 {
  3231.         status = "okay";
  3232. };
  3233.  
  3234. &vpu_h1 {
  3235.         status = "okay";
  3236. };
  3237.  
  3238. &mu {
  3239.         status = "okay";
  3240. };
  3241.  
  3242. &lcd0_backlight {
  3243.         status = "okay";
  3244. };
  3245.  
  3246. &pwm1 {
  3247.         status = "okay";
  3248. };
  3249.  
  3250. &dphy {
  3251.         status = "okay";
  3252. };
  3253. # 18 "arch/arm64/boot/dts/msc/imx8mm/msc-sm2s-imx8mm-14N0261I-headless.dts" 2
  3254.  
  3255. / {
  3256.  leds: leds {
  3257.   compatible = "gpio-leds";
  3258.  
  3259.   led@1 {
  3260.    label = "led_blue";
  3261.    gpios = <&pca 15 0>;
  3262.    linux,default-trigger = "heartbeat";
  3263.   };
  3264.  };
  3265. };
  3266.  
  3267. &i2c3 {
  3268.  edt-ft5x06@38 {
  3269.   compatible = "edt,edt-ft5406", "edt,edt-ft5x06";
  3270.   reg = <0x38>;
  3271.   pinctrl-names = "default";
  3272.   interrupt-parent = <&gpio1>;
  3273.   interrupts = <1 2>;
  3274.   reset-gpios = <&gpio1 9 1>;
  3275.   touchscreen-size-x = <720>;
  3276.   touchscreen-size-y = <1280>;
  3277.  
  3278.  };
  3279.  
  3280.  gt911@5d {
  3281.   compatible = "goodix,gt911";
  3282.   reg = <0x5d>;
  3283.   interrupt-parent = <&gpio1>;
  3284.   interrupts = <1 0>;
  3285.   irq-gpios = <&gpio1 1 0>;
  3286.   touchscreen-inverted-y;
  3287.  };
  3288.  
  3289.  pca: pca@74 {
  3290.   compatible = "nxp,pca9555";
  3291.   reg = <0x74>;
  3292.   gpio-controller;
  3293.   #gpio-cells = <2>;
  3294.   interrupt-parent = <&gpio1>;
  3295.   interrupts = <0 0>;
  3296.   interrupt-controller;
  3297.   status = "okay";
  3298.  };
  3299. };
  3300.  
  3301. &usbotg1 {
  3302.  maximum-speed = "full-speed";
  3303.  dr_mode = "peripheral";
  3304. };
  3305.  

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